Analog to Digital Convertor Peripheral

ADC (AT91S_ADC) 0xFFFD8000 (AT91C_BASE_ADC)
Periph ID AIC Symbol Description
4 (AT91C_ID_ADC)Analog-to-Digital Converter

Signal Symbol PIO controller Description
ADTRG(AT91C_PA8_ADTRG )PIOA Periph: B Bit: 8ADC External Trigger

Function Description
AT91F_ADC_CfgPMCEnable Peripheral clock in PMC for ADC
AT91F_ADC_CfgPIOConfigure PIO controllers to drive ADC signals


ADC Software API (AT91S_ADC)

Offset Field Description
0x0ADC_CRADC Control Register
0x4ADC_MRADC Mode Register
0x10ADC_CHER ( ADC_CHER)ADC Channel Enable Register
0x14ADC_CHDR ( ADC_CHDR)ADC Channel Disable Register
0x18ADC_CHSR ( ADC_CHSR)ADC Channel Status Register
0x1CADC_SRADC Status Register
0x20ADC_LCDRADC Last Converted Data Register
0x24ADC_IERADC Interrupt Enable Register
0x28ADC_IDRADC Interrupt Disable Register
0x2CADC_IMRADC Interrupt Mask Register
0x30ADC_CDR0ADC Channel Data Register 0
0x34ADC_CDR1ADC Channel Data Register 1
0x38ADC_CDR2ADC Channel Data Register 2
0x3CADC_CDR3ADC Channel Data Register 3
0x40ADC_CDR4ADC Channel Data Register 4
0x44ADC_CDR5ADC Channel Data Register 5
0x48ADC_CDR6ADC Channel Data Register 6
0x4CADC_CDR7ADC Channel Data Register 7
0x100ADC_RPR (PDC_RPR)Receive Pointer Register
0x104ADC_RCR (PDC_RCR)Receive Counter Register
0x108ADC_TPR (PDC_TPR)Transmit Pointer Register
0x10CADC_TCR (PDC_TCR)Transmit Counter Register
0x110ADC_RNPR (PDC_RNPR)Receive Next Pointer Register
0x114ADC_RNCR (PDC_RNCR)Receive Next Counter Register
0x118ADC_TNPR (PDC_TNPR)Transmit Next Pointer Register
0x11CADC_TNCR (PDC_TNCR)Transmit Next Counter Register
0x120ADC_PTCR (PDC_PTCR)PDC Transfer Control Register
0x124ADC_PTSR (PDC_PTSR)PDC Transfer Status Register

Function Description
AT91F_ADC_GetConvertedDataCH0Return the Channel 0 Converted Data
AT91F_ADC_GetConvertedDataCH1Return the Channel 1 Converted Data
AT91F_ADC_GetConvertedDataCH2Return the Channel 2 Converted Data
AT91F_ADC_CfgModeRegConfigure the Mode Register of the ADC controller
AT91F_ADC_GetConvertedDataCH3Return the Channel 3 Converted Data
AT91F_ADC_GetConvertedDataCH4Return the Channel 4 Converted Data
AT91F_ADC_GetConvertedDataCH5Return the Channel 5 Converted Data
AT91F_ADC_GetConvertedDataCH6Return the Channel 6 Converted Data
AT91F_ADC_GetConvertedDataCH7Return the Channel 7 Converted Data
AT91F_ADC_GetChannelStatusReturn ADC Timer Register Value
AT91F_ADC_GetModeRegReturn the Mode Register of the ADC controller value
AT91F_ADC_DisableItDisable ADC interrupt
AT91F_ADC_StartConversionSoftware request for a analog to digital conversion
AT91F_ADC_GetStatusReturn ADC Interrupt Status
AT91F_ADC_GetLastConvertedDataReturn the Last Converted Data
AT91F_ADC_SoftResetSoftware reset
AT91F_ADC_CfgTimingsConfigure the different necessary timings of the ADC controller
AT91F_ADC_DisableChannelReturn ADC Timer Register Value
AT91F_ADC_EnableItEnable ADC interrupt
AT91F_ADC_GetInterruptMaskStatusReturn ADC Interrupt Mask Status
AT91F_ADC_IsStatusSetTest if ADC Status is Set
AT91F_ADC_EnableChannelReturn ADC Timer Register Value
AT91F_ADC_IsInterruptMaskedTest if ADC Interrupt is Masked

ADC Register Description

ADC: AT91_REG ADC_CR - ADC Control Register

Offset Name Description
0ADC_SWRST
AT91C_ADC_SWRST
Software Reset
0 = No effect.
1 = Resets the ADC simulating a hardware reset.
1ADC_START
AT91C_ADC_START
Start Conversion
0 = No effect.
1 = Begins analog-to-digital conversion and clears all EOC bits.

ADC: AT91_REG ADC_MR - ADC Mode Register

Offset Name Description
0ADC_TRGEN
AT91C_ADC_TRGEN
Trigger Enable
ValueLabelDescription
0ADC_TRGEN_DIS
AT91C_ADC_TRGEN_DIS

Hradware triggers are disabled. Starting a conversion is only possible by software
1ADC_TRGEN_EN
AT91C_ADC_TRGEN_EN

Hardware trigger selected by TRGSEL field is enabled.
3..1ADC_TRGSEL
AT91C_ADC_TRGSEL
Trigger Selection
ValueLabelDescription
0ADC_TRGSEL_TIOA0
AT91C_ADC_TRGSEL_TIOA0

Selected TRGSEL = TIAO0
1ADC_TRGSEL_TIOA1
AT91C_ADC_TRGSEL_TIOA1

Selected TRGSEL = TIAO1
2ADC_TRGSEL_TIOA2
AT91C_ADC_TRGSEL_TIOA2

Selected TRGSEL = TIAO2
3ADC_TRGSEL_TIOA3
AT91C_ADC_TRGSEL_TIOA3

Selected TRGSEL = TIAO3
4ADC_TRGSEL_TIOA4
AT91C_ADC_TRGSEL_TIOA4

Selected TRGSEL = TIAO4
5ADC_TRGSEL_TIOA5
AT91C_ADC_TRGSEL_TIOA5

Selected TRGSEL = TIAO5
6ADC_TRGSEL_EXT
AT91C_ADC_TRGSEL_EXT

Selected TRGSEL = External Trigger
4ADC_LOWRES
AT91C_ADC_LOWRES
Resolution.
ValueLabelDescription
0ADC_LOWRES_10_BIT
AT91C_ADC_LOWRES_10_BIT

10-bit resolution
1ADC_LOWRES_8_BIT
AT91C_ADC_LOWRES_8_BIT

8-bit resolution
5ADC_SLEEP
AT91C_ADC_SLEEP
Sleep Mode
ValueLabelDescription
0ADC_SLEEP_NORMAL_MODE
AT91C_ADC_SLEEP_NORMAL_MODE

Normal Mode
1ADC_SLEEP_MODE
AT91C_ADC_SLEEP_MODE

Sleep Mode
13..8ADC_PRESCAL
AT91C_ADC_PRESCAL
Prescaler rate selection
This field defines the conversion clock in function of the Master Clcok (MCK).
ADCClock = MCK/((PRESCAL + 1) x 2).
Range = MCK/2 to MCK/128.
20..16ADC_STARTUP
AT91C_ADC_STARTUP
Startup Time
This field defines the necessary startup time in function of the ADC Clock.
Startup Time = (STARTUP+1)* 8 / ADCClock.
27..24ADC_SHTIM
AT91C_ADC_SHTIM
Sample & Hold Time
This field defines the necessary time between 2 channels selection to guarantee the converted value in function of the ADC Clock.
Sample & Hold Time = (SHTIM+1) / ADCClock.

ADC: AT91_REG ADC_CHER - ADC Channel Enable Register


0 = No effect.
1 = Enable the corresponding channel
Offset Name Description
0ADC_CH0
AT91C_ADC_CH0
Channel 0
1ADC_CH1
AT91C_ADC_CH1
Channel 1
2ADC_CH2
AT91C_ADC_CH2
Channel 2
3ADC_CH3
AT91C_ADC_CH3
Channel 3
4ADC_CH4
AT91C_ADC_CH4
Channel 4
5ADC_CH5
AT91C_ADC_CH5
Channel 5
6ADC_CH6
AT91C_ADC_CH6
Channel 6
7ADC_CH7
AT91C_ADC_CH7
Channel 7

ADC: AT91_REG ADC_CHDR - ADC Channel Disable Register


0 = No effect.
1 = Disable the corresponding channel
Offset Name Description
0ADC_CH0
AT91C_ADC_CH0
Channel 0
1ADC_CH1
AT91C_ADC_CH1
Channel 1
2ADC_CH2
AT91C_ADC_CH2
Channel 2
3ADC_CH3
AT91C_ADC_CH3
Channel 3
4ADC_CH4
AT91C_ADC_CH4
Channel 4
5ADC_CH5
AT91C_ADC_CH5
Channel 5
6ADC_CH6
AT91C_ADC_CH6
Channel 6
7ADC_CH7
AT91C_ADC_CH7
Channel 7

ADC: AT91_REG ADC_CHSR - ADC Channel Status Register


0 = Corresponding channel is disabled.
1 = Corresponding channel is enabled
Offset Name Description
0ADC_CH0
AT91C_ADC_CH0
Channel 0
1ADC_CH1
AT91C_ADC_CH1
Channel 1
2ADC_CH2
AT91C_ADC_CH2
Channel 2
3ADC_CH3
AT91C_ADC_CH3
Channel 3
4ADC_CH4
AT91C_ADC_CH4
Channel 4
5ADC_CH5
AT91C_ADC_CH5
Channel 5
6ADC_CH6
AT91C_ADC_CH6
Channel 6
7ADC_CH7
AT91C_ADC_CH7
Channel 7

ADC: AT91_REG ADC_SR - ADC Status Register


EOCx:
0 = Channel x is disabled, or the conversion is not finished.
1 = Channel x is enabled and conversion is complete.
OVREx:
0 = No overrun on the channel x since the last read of ADC_SR.
1 = There has been an overrun on the channel x since the last read of ADC_SR.
DRDY:
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted since the last read of ADC_LCDR.
GOVRE:
0 = No Overrun Error occured since the last read of ADC_LCDR.
1 = At least one Overrun Error has occured since the last read of ADC_LCDR.
ENDBUF:
0 = The PDC does not report an end of buffer.
1 = The PDC reports an end of buffer.
BUFFULL:
0 = The PDC does not report a buffer full.
1 = The PDC reports a buffer full.
Offset Name Description
0ADC_EOC0
AT91C_ADC_EOC0
End of Conversion
1ADC_EOC1
AT91C_ADC_EOC1
End of Conversion
2ADC_EOC2
AT91C_ADC_EOC2
End of Conversion
3ADC_EOC3
AT91C_ADC_EOC3
End of Conversion
4ADC_EOC4
AT91C_ADC_EOC4
End of Conversion
5ADC_EOC5
AT91C_ADC_EOC5
End of Conversion
6ADC_EOC6
AT91C_ADC_EOC6
End of Conversion
7ADC_EOC7
AT91C_ADC_EOC7
End of Conversion
8ADC_OVRE0
AT91C_ADC_OVRE0
Overrun Error
9ADC_OVRE1
AT91C_ADC_OVRE1
Overrun Error
10ADC_OVRE2
AT91C_ADC_OVRE2
Overrun Error
11ADC_OVRE3
AT91C_ADC_OVRE3
Overrun Error
12ADC_OVRE4
AT91C_ADC_OVRE4
Overrun Error
13ADC_OVRE5
AT91C_ADC_OVRE5
Overrun Error
14ADC_OVRE6
AT91C_ADC_OVRE6
Overrun Error
15ADC_OVRE7
AT91C_ADC_OVRE7
Overrun Error
16ADC_DRDY
AT91C_ADC_DRDY
Data Ready
17ADC_GOVRE
AT91C_ADC_GOVRE
General Overrun
18ADC_ENDRX
AT91C_ADC_ENDRX
End of Receiver Transfer
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19ADC_RXBUFF
AT91C_ADC_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.

ADC: AT91_REG ADC_LCDR - ADC Last Converted Data Register

Offset Name Description
9..0ADC_LDATA
AT91C_ADC_LDATA
Last Data Converted
Data converted is placed at the end of conversion and remains until a new one is completed.

ADC: AT91_REG ADC_IER - ADC Interrupt Enable Register


0 = No effect. 1 = Enables the corresponding interrupt.
Offset Name Description
0ADC_EOC0
AT91C_ADC_EOC0
End of Conversion
1ADC_EOC1
AT91C_ADC_EOC1
End of Conversion
2ADC_EOC2
AT91C_ADC_EOC2
End of Conversion
3ADC_EOC3
AT91C_ADC_EOC3
End of Conversion
4ADC_EOC4
AT91C_ADC_EOC4
End of Conversion
5ADC_EOC5
AT91C_ADC_EOC5
End of Conversion
6ADC_EOC6
AT91C_ADC_EOC6
End of Conversion
7ADC_EOC7
AT91C_ADC_EOC7
End of Conversion
8ADC_OVRE0
AT91C_ADC_OVRE0
Overrun Error
9ADC_OVRE1
AT91C_ADC_OVRE1
Overrun Error
10ADC_OVRE2
AT91C_ADC_OVRE2
Overrun Error
11ADC_OVRE3
AT91C_ADC_OVRE3
Overrun Error
12ADC_OVRE4
AT91C_ADC_OVRE4
Overrun Error
13ADC_OVRE5
AT91C_ADC_OVRE5
Overrun Error
14ADC_OVRE6
AT91C_ADC_OVRE6
Overrun Error
15ADC_OVRE7
AT91C_ADC_OVRE7
Overrun Error
16ADC_DRDY
AT91C_ADC_DRDY
Data Ready
17ADC_GOVRE
AT91C_ADC_GOVRE
General Overrun
18ADC_ENDRX
AT91C_ADC_ENDRX
End of Receiver Transfer
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19ADC_RXBUFF
AT91C_ADC_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.

ADC: AT91_REG ADC_IDR - ADC Interrupt Disable Register


0 = No effect. 1 = disables the corresponding interrupt.
Offset Name Description
0ADC_EOC0
AT91C_ADC_EOC0
End of Conversion
1ADC_EOC1
AT91C_ADC_EOC1
End of Conversion
2ADC_EOC2
AT91C_ADC_EOC2
End of Conversion
3ADC_EOC3
AT91C_ADC_EOC3
End of Conversion
4ADC_EOC4
AT91C_ADC_EOC4
End of Conversion
5ADC_EOC5
AT91C_ADC_EOC5
End of Conversion
6ADC_EOC6
AT91C_ADC_EOC6
End of Conversion
7ADC_EOC7
AT91C_ADC_EOC7
End of Conversion
8ADC_OVRE0
AT91C_ADC_OVRE0
Overrun Error
9ADC_OVRE1
AT91C_ADC_OVRE1
Overrun Error
10ADC_OVRE2
AT91C_ADC_OVRE2
Overrun Error
11ADC_OVRE3
AT91C_ADC_OVRE3
Overrun Error
12ADC_OVRE4
AT91C_ADC_OVRE4
Overrun Error
13ADC_OVRE5
AT91C_ADC_OVRE5
Overrun Error
14ADC_OVRE6
AT91C_ADC_OVRE6
Overrun Error
15ADC_OVRE7
AT91C_ADC_OVRE7
Overrun Error
16ADC_DRDY
AT91C_ADC_DRDY
Data Ready
17ADC_GOVRE
AT91C_ADC_GOVRE
General Overrun
18ADC_ENDRX
AT91C_ADC_ENDRX
End of Receiver Transfer
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19ADC_RXBUFF
AT91C_ADC_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.

ADC: AT91_REG ADC_IMR - ADC Interrupt Mask Register


0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
Offset Name Description
0ADC_EOC0
AT91C_ADC_EOC0
End of Conversion
1ADC_EOC1
AT91C_ADC_EOC1
End of Conversion
2ADC_EOC2
AT91C_ADC_EOC2
End of Conversion
3ADC_EOC3
AT91C_ADC_EOC3
End of Conversion
4ADC_EOC4
AT91C_ADC_EOC4
End of Conversion
5ADC_EOC5
AT91C_ADC_EOC5
End of Conversion
6ADC_EOC6
AT91C_ADC_EOC6
End of Conversion
7ADC_EOC7
AT91C_ADC_EOC7
End of Conversion
8ADC_OVRE0
AT91C_ADC_OVRE0
Overrun Error
9ADC_OVRE1
AT91C_ADC_OVRE1
Overrun Error
10ADC_OVRE2
AT91C_ADC_OVRE2
Overrun Error
11ADC_OVRE3
AT91C_ADC_OVRE3
Overrun Error
12ADC_OVRE4
AT91C_ADC_OVRE4
Overrun Error
13ADC_OVRE5
AT91C_ADC_OVRE5
Overrun Error
14ADC_OVRE6
AT91C_ADC_OVRE6
Overrun Error
15ADC_OVRE7
AT91C_ADC_OVRE7
Overrun Error
16ADC_DRDY
AT91C_ADC_DRDY
Data Ready
17ADC_GOVRE
AT91C_ADC_GOVRE
General Overrun
18ADC_ENDRX
AT91C_ADC_ENDRX
End of Receiver Transfer
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19ADC_RXBUFF
AT91C_ADC_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.

ADC: AT91_REG ADC_CDR0 - ADC Channel Data Register 0

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR1 - ADC Channel Data Register 1

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR2 - ADC Channel Data Register 2

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR3 - ADC Channel Data Register 3

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR4 - ADC Channel Data Register 4

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR5 - ADC Channel Data Register 5

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR6 - ADC Channel Data Register 6

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91_REG ADC_CDR7 - ADC Channel Data Register 7

Offset Name Description
9..0ADC_DATA
AT91C_ADC_DATA
Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

ADC: AT91S_PDC ADC_PDC - PDC interface