Advanced Interrupt Controller Peripheral

Periph ID AIC Symbol Description
0 (AT91C_ID_FIQ)Advanced Interrupt Controller (FIQ)
30 (AT91C_ID_IRQ0)Advanced Interrupt Controller (IRQ0)
31 (AT91C_ID_IRQ1)Advanced Interrupt Controller (IRQ1)

Signal Symbol PIO controller Description
IRQ0(AT91C_PA20_IRQ0 )PIOA Periph: B Bit: 20External Interrupt 0
FIQ(AT91C_PA19_FIQ )PIOA Periph: B Bit: 19AIC Fast Interrupt Input
IRQ1(AT91C_PA30_IRQ1 )PIOA Periph: A Bit: 30External Interrupt 1

Function Description
AT91F_AIC_CfgPIOConfigure PIO controllers to drive AIC signals
AT91F_AIC_CfgPMCEnable Peripheral clock in PMC for AIC

AIC Software API (AT91S_AIC)

Offset Field Description
0x0AIC_SMR[32] (AIC_SMR)Source Mode Register
0x80AIC_SVR[32] (AIC_SVR)Source Vector Register
0x100AIC_IVRIRQ Vector Register
0x104AIC_FVRFIQ Vector Register
0x108AIC_ISRInterrupt Status Register
0x10CAIC_IPRInterrupt Pending Register
0x110AIC_IMRInterrupt Mask Register
0x114AIC_CISRCore Interrupt Status Register
0x120AIC_IECRInterrupt Enable Command Register
0x124AIC_IDCRInterrupt Disable Command Register
0x128AIC_ICCRInterrupt Clear Command Register
0x12CAIC_ISCRInterrupt Set Command Register
0x130AIC_EOICREnd of Interrupt Command Register
0x134AIC_SPUSpurious Vector Register
0x138AIC_DCRDebug Control Register (Protect)
0x140AIC_FFERFast Forcing Enable Register
0x144AIC_FFDRFast Forcing Disable Register
0x148AIC_FFSRFast Forcing Status Register

Function Description
AT91F_AIC_SetExceptionVectorConfigure vector handler
AT91F_AIC_ClearItClear corresponding IT number
AT91F_AIC_TrigTrig an IT
AT91F_AIC_OpenSet exception vectors and AIC registers to default values
AT91F_AIC_DisableItDisable corresponding IT number
AT91F_AIC_AcknowledgeItAcknowledge corresponding IT number
AT91F_AIC_ConfigureItInterrupt Handler Initialization
AT91F_AIC_EnableItEnable corresponding IT number
AT91F_AIC_IsActiveTest if an IT is active
AT91F_AIC_IsPendingTest if an IT is pending

AIC Register Description

AIC: AT91_REG AIC_SMR - Source Mode Register

Offset Name Description
Priority Level
Program the priority level for all sources except source 0 (FIQ).
The priority level can be between 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ, in the SMR0.

Lowest priority level

Highest priority level
Interrupt Source Type
Program the input to be positive or negative edge-triggered or positive or negative level sensitive.
The active level or edge is not programmable for the internal sources.

Internal Sources Code Label Level Sensitive

Internal Sources Code Label Edge triggered

External Sources Code Label High-level Sensitive

External Sources Code Label Positive Edge triggered

AIC: AT91_REG AIC_SVR - Source Vector Register

The user may store in these registers the addresses of the corresponding handler for each interrupt source.

AIC: AT91_REG AIC_IVR - IRQ Vector Register

The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to
the current interrupt.
The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read.
When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU.

AIC: AT91_REG AIC_FVR - FIQ Vector Register

The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corre-sponds to FIQ.

AIC: AT91_REG AIC_ISR - Interrupt Status Register

The Interrupt Status Register returns the current interrupt source number.

AIC: AT91_REG AIC_IPR - Interrupt Pending Register

0 = Corresponding interrupt is inactive.
1 = Corresponding interrupt is pending.

AIC: AT91_REG AIC_IMR - Interrupt Mask Register

0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.

AIC: AT91_REG AIC_CISR - Core Interrupt Status Register

Offset Name Description
NFIQ Status
0 = NFIQ line inactive.
1 = NFIQ line active.
NIRQ Status
0 = NIRQ line inactive.
1 = NIRQ line active.

AIC: AT91_REG AIC_IECR - Interrupt Enable Command Register

0 = No effect.
1 = Enables corresponding interrupt.

AIC: AT91_REG AIC_IDCR - Interrupt Disable Command Register

0 = No effect.
1 = Disables corresponding interrupt.

AIC: AT91_REG AIC_ICCR - Interrupt Clear Command Register

0 = No effect.
1 = Clears corresponding interrupt.

AIC: AT91_REG AIC_ISCR - Interrupt Set Command Register

0 = No effect.
1 = Sets corresponding interrupt.

AIC: AT91_REG AIC_EOICR - End of Interrupt Command Register

The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt

AIC: AT91_REG AIC_SPU - Spurious Vector Register

Spurious Interrupt Vector Handler Address
The user may store the address of the spurious interrupt handler in this register.

AIC: AT91_REG AIC_DCR - Debug Control Register (Protect)

Offset Name Description
Protection Mode
0: The protection Mode is disabled
1: The Protection mode is enabled
General Mask
0: The nIRQ qnd nFIQ lines are normally controled by the AIC
1: The nIRQ and nFIQ lines are tied to their inactive mode

AIC: AT91_REG AIC_FFER - Fast Forcing Enable Register

0 = No effect.
1 = Enables fast forcing feature on corresponding interrupt.

AIC: AT91_REG AIC_FFDR - Fast Forcing Disable Register

0 = No effect.
1 = Disables fast forcing feature on corresponding interrupt.

AIC: AT91_REG AIC_FFSR - Fast Forcing Status Register

0 = Disabled.
1 = Fast forcing feature enabled on corresponding interrupt.