Clock Generator Controler Peripheral

CKGR (AT91S_CKGR) 0xFFFFFC20 (AT91C_BASE_CKGR)

CKGR Software API (AT91S_CKGR)

Offset Field Description
0x0CKGR_MORMain Oscillator Register
0x4CKGR_MCFRMain Clock Frequency Register
0xCCKGR_PLLRPLL Register

CKGR Register Description

CKGR: AT91_REG CKGR_MOR - Main Oscillator Register

Offset Name Description
0CKGR_MOSCEN
AT91C_CKGR_MOSCEN
Main Oscillator Enable
0 = The main oscillator is disabled.
1 = The main oscillator is enabled.
1CKGR_OSCBYPASS
AT91C_CKGR_OSCBYPASS
Main Oscillator Bypass
0 = The main oscillator is not bypassed.
1 = The main oscillator is bypassed. MOSCEN bit must be set to 0.
15..8CKGR_OSCOUNT
AT91C_CKGR_OSCOUNT
Main Oscillator Start-up Time
Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.

CKGR: AT91_REG CKGR_MCFR - Main Clock Frequency Register

Offset Name Description
15..0CKGR_MAINF
AT91C_CKGR_MAINF
Main Clock Frequency
Gives the number of main clock cycles within 16 slow clock periods.
16CKGR_MAINRDY
AT91C_CKGR_MAINRDY
Main Clock Ready
0 = FMAIN value is not valid or the main oscillator is disabled.
1 = The main oscillator has been enabled previously and MAINF value is available.

CKGR: AT91_REG CKGR_PLLR - PLL Register

Offset Name Description
7..0CKGR_DIV
AT91C_CKGR_DIV
Divider Selected
2-255 Divider output is the selected clock divided by DIV
ValueLabelDescription
0CKGR_DIV_0
AT91C_CKGR_DIV_0

Divider output is 0
1CKGR_DIV_BYPASS
AT91C_CKGR_DIV_BYPASS

Divider is bypassed
13..8CKGR_PLLCOUNT
AT91C_CKGR_PLLCOUNT
PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in APMC_SR after APMC_PLL is written.
15..14CKGR_OUT
AT91C_CKGR_OUT
PLL Output Frequency Range
ValueLabelDescription
0CKGR_OUT_0
AT91C_CKGR_OUT_0

Please refer to the PLL datasheet
1CKGR_OUT_1
AT91C_CKGR_OUT_1

Please refer to the PLL datasheet
2CKGR_OUT_2
AT91C_CKGR_OUT_2

Please refer to the PLL datasheet
3CKGR_OUT_3
AT91C_CKGR_OUT_3

Please refer to the PLL datasheet
26..16CKGR_MUL
AT91C_CKGR_MUL
PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL output frequency is the PLL input frequency multiplied by MUL + 1.
29..28CKGR_USBDIV
AT91C_CKGR_USBDIV
Divider for USB Clocks
ValueLabelDescription
0CKGR_USBDIV_0
AT91C_CKGR_USBDIV_0

Divider output is PLL clock output
1CKGR_USBDIV_1
AT91C_CKGR_USBDIV_1

Divider output is PLL clock output divided by 2
2CKGR_USBDIV_2
AT91C_CKGR_USBDIV_2

Divider output is PLL clock output divided by 4