|0x0||CKGR_MOR||Main Oscillator Register|
|0x4||CKGR_MCFR||Main Clock Frequency Register|
|Main Oscillator Enable|
0 = The main oscillator is disabled.
1 = The main oscillator is enabled.
|Main Oscillator Bypass|
0 = The main oscillator is not bypassed.
1 = The main oscillator is bypassed. MOSCEN bit must be set to 0.
|Main Oscillator Start-up Time|
Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.
|Main Clock Frequency|
Gives the number of main clock cycles within 16 slow clock periods.
|Main Clock Ready|
0 = FMAIN value is not valid or the main oscillator is disabled.
1 = The main oscillator has been enabled previously and MAINF value is available.
2-255 Divider output is the selected clock divided by DIV
Specifies the number of slow clock cycles before the LOCK bit is set in APMC_SR after APMC_PLL is written.
|PLL Output Frequency Range|
0 = The PLL is deactivated.
1 up to 2047 = The PLL output frequency is the PLL input frequency multiplied by MUL + 1.
|Divider for USB Clocks|