Pulse Width Modulation Controller Interface Peripheral

PWMC (AT91S_PWMC) 0xFFFCC000 (AT91C_BASE_PWMC)
Periph ID AIC Symbol Description
10 (AT91C_ID_PWMC)PWM Controller

Function Description
AT91F_PWMC_CfgPMCEnable Peripheral clock in PMC for PWMC


PWMC Software API (AT91S_PWMC)

Offset Field Description
0x0PWMC_MRPWMC Mode Register
0x4PWMC_ENAPWMC Enable Register
0x8PWMC_DISPWMC Disable Register
0xCPWMC_SRPWMC Status Register
0x10PWMC_IERPWMC Interrupt Enable Register
0x14PWMC_IDRPWMC Interrupt Disable Register
0x18PWMC_IMRPWMC Interrupt Mask Register
0x1CPWMC_ISRPWMC Interrupt Status Register
0xFCPWMC_VRPWMC Version Register
0x200PWMC_CH[32] (PWMC_CH)PWMC Channel 0

Function Description
AT91F_PWM_StopChannelDisable channel
AT91F_PWM_GetStatusReturn PWM Interrupt Status
AT91F_PWM_CfgChannelTest if PWM Interrupt is Set
AT91F_PWM_IsInterruptMaskedTest if PWM Interrupt is Masked
AT91F_PWM_InterruptEnableEnable PWM Interrupt
AT91F_PWM_InterruptDisableDisable PWM Interrupt
AT91F_PWM_IsStatusSetTest if PWM Interrupt is Set
AT91F_PWM_StartChannelEnable channel
AT91F_PWM_UpdateChannelUpdate Period or Duty Cycle
AT91F_PWM_GetInterruptMaskStatusReturn PWM Interrupt Mask Status

PWMC Register Description

PWMC: AT91_REG PWMC_MR - PWMC Mode Register

Offset Name Description
7..0PWMC_DIVA
AT91C_PWMC_DIVA
CLKA divide factor.
11..8PWMC_PREA
AT91C_PWMC_PREA
Divider Input Clock Prescaler A
ValueLabelDescription
0PWMC_PREA_MCK
AT91C_PWMC_PREA_MCK
1PWMC_PREA_MCK/2
AT91C_PWMC_PREA_MCK/2
2PWMC_PREA_MCK/4
AT91C_PWMC_PREA_MCK/4
3PWMC_PREA_MCK/8
AT91C_PWMC_PREA_MCK/8
4PWMC_PREA_MCK/16
AT91C_PWMC_PREA_MCK/16
5PWMC_PREA_MCK/32
AT91C_PWMC_PREA_MCK/32
6PWMC_PREA_MCK/64
AT91C_PWMC_PREA_MCK/64
7PWMC_PREA_MCK/128
AT91C_PWMC_PREA_MCK/128
8PWMC_PREA_MCK/256
AT91C_PWMC_PREA_MCK/256
23..16PWMC_DIVB
AT91C_PWMC_DIVB
CLKB divide factor.
27..24PWMC_PREB
AT91C_PWMC_PREB
Divider Input Clock Prescaler B
ValueLabelDescription
0PWMC_PREB_MCK
AT91C_PWMC_PREB_MCK
1PWMC_PREB_MCK/2
AT91C_PWMC_PREB_MCK/2
2PWMC_PREB_MCK/4
AT91C_PWMC_PREB_MCK/4
3PWMC_PREB_MCK/8
AT91C_PWMC_PREB_MCK/8
4PWMC_PREB_MCK/16
AT91C_PWMC_PREB_MCK/16
5PWMC_PREB_MCK/32
AT91C_PWMC_PREB_MCK/32
6PWMC_PREB_MCK/64
AT91C_PWMC_PREB_MCK/64
7PWMC_PREB_MCK/128
AT91C_PWMC_PREB_MCK/128
8PWMC_PREB_MCK/256
AT91C_PWMC_PREB_MCK/256

PWMC: AT91_REG PWMC_ENA - PWMC Enable Register


Enable PWMC output for the corresponding channel
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_DIS - PWMC Disable Register


Disable PWMC output for the corresponding channel
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_SR - PWMC Status Register


0: PWMC output for channel X is disabled.
1: PWMC output for channel X is enabled.
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_IER - PWMC Interrupt Enable Register


0: No effect.
1: Enable Interrupt for PWMC channel X.
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_IDR - PWMC Interrupt Disable Register


0: No effect.
1: Disable Interrupt for PWMC channel X.
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_IMR - PWMC Interrupt Mask Register


0: Interrupt for PWMC channel X is disabled.
1: Interrupt for PWMC channel X is enabled.
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_ISR - PWMC Interrupt Status Register


0: No Interrupt for PWMC channel X pending. 1: Interrupt for PWMC channel X has raised.
Offset Name Description
0PWMC_CHID0
AT91C_PWMC_CHID0
Channel ID 0
1PWMC_CHID1
AT91C_PWMC_CHID1
Channel ID 1
2PWMC_CHID2
AT91C_PWMC_CHID2
Channel ID 2
3PWMC_CHID3
AT91C_PWMC_CHID3
Channel ID 3
4PWMC_CHID4
AT91C_PWMC_CHID4
Channel ID 4
5PWMC_CHID5
AT91C_PWMC_CHID5
Channel ID 5
6PWMC_CHID6
AT91C_PWMC_CHID6
Channel ID 6
7PWMC_CHID7
AT91C_PWMC_CHID7
Channel ID 7

PWMC: AT91_REG PWMC_VR - PWMC Version Register

PWMC: AT91S_PWMC_CH PWMC_CH - PWMC Channel 0