Synchronous Serial Controller Interface Peripheral

SSC (AT91S_SSC) 0xFFFD4000 (AT91C_BASE_SSC)
Periph ID AIC Symbol Description
8 (AT91C_ID_SSC)Serial Synchronous Controller

Signal Symbol PIO controller Description
TD(AT91C_PA17_TD )PIOA Periph: A Bit: 17SSC Transmit data
TF(AT91C_PA15_TF )PIOA Periph: A Bit: 15SSC Transmit Frame Sync
RK(AT91C_PA19_RK )PIOA Periph: A Bit: 19SSC Receive Clock
RD(AT91C_PA18_RD )PIOA Periph: A Bit: 18SSC Receive Data
RF(AT91C_PA20_RF )PIOA Periph: A Bit: 20SSC Receive Frame Sync
TK(AT91C_PA16_TK )PIOA Periph: A Bit: 16SSC Transmit Clock

Function Description
AT91F_SSC_CfgPIOConfigure PIO controllers to drive SSC signals
AT91F_SSC_CfgPMCEnable Peripheral clock in PMC for SSC


SSC Software API (AT91S_SSC)

Offset Field Description
0x0SSC_CRControl Register
0x4SSC_CMRClock Mode Register
0x10SSC_RCMRReceive Clock ModeRegister
0x14SSC_RFMRReceive Frame Mode Register
0x18SSC_TCMRTransmit Clock Mode Register
0x1CSSC_TFMRTransmit Frame Mode Register
0x20SSC_RHRReceive Holding Register
0x24SSC_THRTransmit Holding Register
0x30SSC_RSHRReceive Sync Holding Register
0x34SSC_TSHRTransmit Sync Holding Register
0x38SSC_RC0RReceive Compare 0 Register
0x3CSSC_RC1RReceive Compare 1 Register
0x40SSC_SRStatus Register
0x44SSC_IERInterrupt Enable Register
0x48SSC_IDRInterrupt Disable Register
0x4CSSC_IMRInterrupt Mask Register
0x100SSC_RPR (PDC_RPR)Receive Pointer Register
0x104SSC_RCR (PDC_RCR)Receive Counter Register
0x108SSC_TPR (PDC_TPR)Transmit Pointer Register
0x10CSSC_TCR (PDC_TCR)Transmit Counter Register
0x110SSC_RNPR (PDC_RNPR)Receive Next Pointer Register
0x114SSC_RNCR (PDC_RNCR)Receive Next Counter Register
0x118SSC_TNPR (PDC_TNPR)Transmit Next Pointer Register
0x11CSSC_TNCR (PDC_TNCR)Transmit Next Counter Register
0x120SSC_PTCR (PDC_PTCR)PDC Transfer Control Register
0x124SSC_PTSR (PDC_PTSR)PDC Transfer Status Register

Function Description
AT91F_SSC_ConfigureConfigure SSC
AT91F_SSC_DisableRxDisable receiving datas
AT91F_SSC_SendFrameReturn 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
AT91F_SSC_DisableItDisable SSC IT
AT91F_SSC_EnableRxEnable receiving datas
AT91F_SSC_ReceiveFrameReturn 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
AT91F_SSC_EnableItEnable SSC IT
AT91F_SSC_SetBaudrateSet the baudrate according to the CPU clock
AT91F_SSC_IsInterruptMaskedTest if SSC Interrupt is Masked
AT91F_SSC_GetInterruptMaskStatusReturn SSC Interrupt Mask Status
AT91F_SSC_DisableTxDisable sending datas
AT91F_SSC_EnableTxEnable sending datas

SSC Register Description

SSC: AT91_REG SSC_CR - Control Register

Offset Name Description
0SSC_RXEN
AT91C_SSC_RXEN
Receive Enable
0: No effect.
1: Enables Receive if RXDIS is not set.
1SSC_RXDIS
AT91C_SSC_RXDIS
Receive Disable
0: No effect.
1: Disables Receive.
8SSC_TXEN
AT91C_SSC_TXEN
Transmit Enable
0: No effect.
1: Enables Transmit if TXDIS is not set.
9SSC_TXDIS
AT91C_SSC_TXDIS
Transmit Disable
0: No effect.
1: Disables Transmit.
15SSC_SWRST
AT91C_SSC_SWRST
Software Reset
0: No effect.
1: Performs a software reset. Has priority on any other bit in SSC_CR.

SSC: AT91_REG SSC_CMR - Clock Mode Register


Clock Divider
0: The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.

SSC: AT91_REG SSC_RCMR - Receive Clock ModeRegister

Offset Name Description
1..0SSC_CKS
AT91C_SSC_CKS
Receive/Transmit Clock Selection
ValueLabelDescription
0SSC_CKS_DIV
AT91C_SSC_CKS_DIV

Divided Clock
1SSC_CKS_TK
AT91C_SSC_CKS_TK

TK Clock signal
2SSC_CKS_RK
AT91C_SSC_CKS_RK

RK pin
4..2SSC_CKO
AT91C_SSC_CKO
Receive/Transmit Clock Output Mode Selection
ValueLabelDescription
0SSC_CKO_NONE
AT91C_SSC_CKO_NONE

Receive/Transmit Clock Output Mode: None RK pin: Input-only
1SSC_CKO_CONTINOUS
AT91C_SSC_CKO_CONTINOUS

Continuous Receive/Transmit Clock RK pin: Output
2SSC_CKO_DATA_TX
AT91C_SSC_CKO_DATA_TX

Receive/Transmit Clock only during data transfers RK pin: Output
5SSC_CKI
AT91C_SSC_CKI
Receive/Transmit Clock Inversion
0: The data and the Frame Sync signal are sampled on Receive Clock falling edge.
1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge.
CKI affects only the Receive Clock and not the output clock signal.
7..6SSC_CKG
AT91C_SSC_CKG
Receive/Transmit Clock Gating Selection
ValueLabelDescription
0SSC_CKG_NONE
AT91C_SSC_CKG_NONE

Receive/Transmit Clock Gating: None, continuous clock
1SSC_CKG_LOW
AT91C_SSC_CKG_LOW

Receive/Transmit Clock enabled only if RF Low
2SSC_CKG_HIGH
AT91C_SSC_CKG_HIGH

Receive/Transmit Clock enabled only if RF High
11..8SSC_START
AT91C_SSC_START
Receive/Transmit Start Selection
ValueLabelDescription
0SSC_START_CONTINOUS
AT91C_SSC_START_CONTINOUS

Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
1SSC_START_TX
AT91C_SSC_START_TX

Transmit/Receive start
2SSC_START_LOW_RF
AT91C_SSC_START_LOW_RF

Detection of a low level on RF input
3SSC_START_HIGH_RF
AT91C_SSC_START_HIGH_RF

Detection of a high level on RF input
4SSC_START_FALL_RF
AT91C_SSC_START_FALL_RF

Detection of a falling edge on RF input
5SSC_START_RISE_RF
AT91C_SSC_START_RISE_RF

Detection of a rising edge on RF input
6SSC_START_LEVEL_RF
AT91C_SSC_START_LEVEL_RF

Detection of any level change on RF input
7SSC_START_EDGE_RF
AT91C_SSC_START_EDGE_RF

Detection of any edge on RF input
8SSC_START_0
AT91C_SSC_START_0

Compare 0
12SSC_STOP
AT91C_SSC_STOP
Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
15SSC_STTOUT
AT91C_SSC_STTOUT
Receive/Transmit Start Output Selection
This bit permits the physical avoidance of generating the Receive/Transmit Frame Sync signal if it is not required.
0: Start is detected on the RF input signal coming from the RF pin.
1: Start is detected on the RF output signal generated by the Frame Sync Controller.
23..16SSC_STTDLY
AT91C_SSC_STTDLY
Receive/Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception/transmission.
When the Receiver/Transmitter is programmed to start synchronously with the Transmitter/Receiver, the delay is also applied.
Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive/Transmit Sync Data) reception.
31..24SSC_PERIOD
AT91C_SSC_PERIOD
Receive/Transmit Period Divider Selection
This field selects the divider to apply to the selected Receive/Transmit Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive/Transmit Clock.

SSC: AT91_REG SSC_RFMR - Receive Frame Mode Register

Offset Name Description
4..0SSC_DATLEN
AT91C_SSC_DATLEN
Data Length
The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver/Transmitter. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.
5SSC_LOOP
AT91C_SSC_LOOP
Loop Mode
0: Normal operating mode.
1: RD is driven by TD, RF is driven by TF and TK drives RK.
7SSC_MSBF
AT91C_SSC_MSBF
Most Significant Bit First
0: The lowest significant bit of the data register is sampled first in the bit stream.
1: The most significant bit of the data register is sampled first in the bit stream.
11..8SSC_DATNB
AT91C_SSC_DATNB
Data Number per Frame
This field defines the number of data words to be received/transfered after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred.
19..16SSC_FSLEN
AT91C_SSC_FSLEN
Receive/Transmit Frame Sync length
Receive:
This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. If 0, the Receive Frame Sync Sig-nal is generated during one Receive Clock period and up to a 16-clock period pulse length is possible.
Transmit:
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible.
22..20SSC_FSOS
AT91C_SSC_FSOS
Receive/Transmit Frame Sync Output Selection
ValueLabelDescription
0SSC_FSOS_NONE
AT91C_SSC_FSOS_NONE

Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
1SSC_FSOS_NEGATIVE
AT91C_SSC_FSOS_NEGATIVE

Selected Receive/Transmit Frame Sync Signal: Negative Pulse
2SSC_FSOS_POSITIVE
AT91C_SSC_FSOS_POSITIVE

Selected Receive/Transmit Frame Sync Signal: Positive Pulse
3SSC_FSOS_LOW
AT91C_SSC_FSOS_LOW

Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
4SSC_FSOS_HIGH
AT91C_SSC_FSOS_HIGH

Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
5SSC_FSOS_TOGGLE
AT91C_SSC_FSOS_TOGGLE

Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
24SSC_FSEDGE
AT91C_SSC_FSEDGE
Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN/TXSYN in the SSC Status Register.
0: Positive Edge Detection
1: Negative Edge Detection

SSC: AT91_REG SSC_TCMR - Transmit Clock Mode Register

Offset Name Description
1..0SSC_CKS
AT91C_SSC_CKS
Receive/Transmit Clock Selection
ValueLabelDescription
0SSC_CKS_DIV
AT91C_SSC_CKS_DIV

Divided Clock
1SSC_CKS_TK
AT91C_SSC_CKS_TK

TK Clock signal
2SSC_CKS_RK
AT91C_SSC_CKS_RK

RK pin
4..2SSC_CKO
AT91C_SSC_CKO
Receive/Transmit Clock Output Mode Selection
ValueLabelDescription
0SSC_CKO_NONE
AT91C_SSC_CKO_NONE

Receive/Transmit Clock Output Mode: None RK pin: Input-only
1SSC_CKO_CONTINOUS
AT91C_SSC_CKO_CONTINOUS

Continuous Receive/Transmit Clock RK pin: Output
2SSC_CKO_DATA_TX
AT91C_SSC_CKO_DATA_TX

Receive/Transmit Clock only during data transfers RK pin: Output
5SSC_CKI
AT91C_SSC_CKI
Receive/Transmit Clock Inversion
0: The data and the Frame Sync signal are sampled on Receive Clock falling edge.
1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge.
CKI affects only the Receive Clock and not the output clock signal.
7..6SSC_CKG
AT91C_SSC_CKG
Receive/Transmit Clock Gating Selection
ValueLabelDescription
0SSC_CKG_NONE
AT91C_SSC_CKG_NONE

Receive/Transmit Clock Gating: None, continuous clock
1SSC_CKG_LOW
AT91C_SSC_CKG_LOW

Receive/Transmit Clock enabled only if RF Low
2SSC_CKG_HIGH
AT91C_SSC_CKG_HIGH

Receive/Transmit Clock enabled only if RF High
11..8SSC_START
AT91C_SSC_START
Receive/Transmit Start Selection
ValueLabelDescription
0SSC_START_CONTINOUS
AT91C_SSC_START_CONTINOUS

Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
1SSC_START_TX
AT91C_SSC_START_TX

Transmit/Receive start
2SSC_START_LOW_RF
AT91C_SSC_START_LOW_RF

Detection of a low level on RF input
3SSC_START_HIGH_RF
AT91C_SSC_START_HIGH_RF

Detection of a high level on RF input
4SSC_START_FALL_RF
AT91C_SSC_START_FALL_RF

Detection of a falling edge on RF input
5SSC_START_RISE_RF
AT91C_SSC_START_RISE_RF

Detection of a rising edge on RF input
6SSC_START_LEVEL_RF
AT91C_SSC_START_LEVEL_RF

Detection of any level change on RF input
7SSC_START_EDGE_RF
AT91C_SSC_START_EDGE_RF

Detection of any edge on RF input
8SSC_START_0
AT91C_SSC_START_0

Compare 0
15SSC_STTOUT
AT91C_SSC_STTOUT
Receive/Transmit Start Output Selection
This bit permits the physical avoidance of generating the Receive/Transmit Frame Sync signal if it is not required.
0: Start is detected on the RF input signal coming from the RF pin.
1: Start is detected on the RF output signal generated by the Frame Sync Controller.
23..16SSC_STTDLY
AT91C_SSC_STTDLY
Receive/Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception/transmission.
When the Receiver/Transmitter is programmed to start synchronously with the Transmitter/Receiver, the delay is also applied.
Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive/Transmit Sync Data) reception.
31..24SSC_PERIOD
AT91C_SSC_PERIOD
Receive/Transmit Period Divider Selection
This field selects the divider to apply to the selected Receive/Transmit Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive/Transmit Clock.

SSC: AT91_REG SSC_TFMR - Transmit Frame Mode Register

Offset Name Description
4..0SSC_DATLEN
AT91C_SSC_DATLEN
Data Length
The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver/Transmitter. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.
5SSC_DATDEF
AT91C_SSC_DATDEF
Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1.
7SSC_MSBF
AT91C_SSC_MSBF
Most Significant Bit First
0: The lowest significant bit of the data register is sampled first in the bit stream.
1: The most significant bit of the data register is sampled first in the bit stream.
11..8SSC_DATNB
AT91C_SSC_DATNB
Data Number per Frame
This field defines the number of data words to be received/transfered after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred.
19..16SSC_FSLEN
AT91C_SSC_FSLEN
Receive/Transmit Frame Sync length
Receive:
This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. If 0, the Receive Frame Sync Sig-nal is generated during one Receive Clock period and up to a 16-clock period pulse length is possible.
Transmit:
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible.
22..20SSC_FSOS
AT91C_SSC_FSOS
Receive/Transmit Frame Sync Output Selection
ValueLabelDescription
0SSC_FSOS_NONE
AT91C_SSC_FSOS_NONE

Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
1SSC_FSOS_NEGATIVE
AT91C_SSC_FSOS_NEGATIVE

Selected Receive/Transmit Frame Sync Signal: Negative Pulse
2SSC_FSOS_POSITIVE
AT91C_SSC_FSOS_POSITIVE

Selected Receive/Transmit Frame Sync Signal: Positive Pulse
3SSC_FSOS_LOW
AT91C_SSC_FSOS_LOW

Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
4SSC_FSOS_HIGH
AT91C_SSC_FSOS_HIGH

Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
5SSC_FSOS_TOGGLE
AT91C_SSC_FSOS_TOGGLE

Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
23SSC_FSDEN
AT91C_SSC_FSDEN
Frame Sync Data Enable
0: The TD line is driven with the default value during the Transmit Frame Sync signal.
1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
24SSC_FSEDGE
AT91C_SSC_FSEDGE
Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN/TXSYN in the SSC Status Register.
0: Positive Edge Detection
1: Negative Edge Detection

SSC: AT91_REG SSC_RHR - Receive Holding Register


Right aligned regardless of the number of data bits defined by DATLEN in SSC_RMR

SSC: AT91_REG SSC_THR - Transmit Holding Register


Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR

SSC: AT91_REG SSC_RSHR - Receive Sync Holding Register


Receive Synchronization Data

SSC: AT91_REG SSC_TSHR - Transmit Sync Holding Register


Transmit Synchronization Data

SSC: AT91_REG SSC_RC0R - Receive Compare 0 Register


Receive Compare Data 0

SSC: AT91_REG SSC_RC1R - Receive Compare 1 Register


Receive Compare Data 1

SSC: AT91_REG SSC_SR - Status Register

Offset Name Description
0SSC_TXRDY
AT91C_SSC_TXRDY
Transmit Ready
0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1: SSC_THR is empty.
1SSC_TXEMPTY
AT91C_SSC_TXEMPTY
Transmit Empty
0: Data remains in SSC_THR or is currently transmitted from TSR.
1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
2SSC_ENDTX
AT91C_SSC_ENDTX
End Of Transmission
0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
3SSC_TXBUFE
AT91C_SSC_TXBUFE
Transmit Buffer Empty
0: SSC_TCR or SSC_TNCR have a value other than 0.
1: Both SSC_TCR and SSC_TNCR have a value of 0.
4SSC_RXRDY
AT91C_SSC_RXRDY
Receive Ready
0: SSC_RHR is empty.
1: Data has been received and loaded in SSC_RHR.
5SSC_OVRUN
AT91C_SSC_OVRUN
Receive Overrun
0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.
1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
6SSC_ENDRX
AT91C_SSC_ENDRX
End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
1: End of PDC transfer when Receive Counter Register has arrived at zero.
7SSC_RXBUFF
AT91C_SSC_RXBUFF
Receive Buffer Full
0: SSC_RCR or SSC_RNCR have a value other than 0.
1: Both SSC_RCR and SSC_RNCR have a value of 0.
8SSC_CP0
AT91C_SSC_CP0
Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
9SSC_CP1
AT91C_SSC_CP1
Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
10SSC_TXSYN
AT91C_SSC_TXSYN
Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
11SSC_RXSYN
AT91C_SSC_RXSYN
Receive Sync
0: A Rx Sync has not occurred since the last read of the Status Register.
1: A Rx Sync has occurred since the last read of the Status Register.
16SSC_TXENA
AT91C_SSC_TXENA
Transmit Enable
0: Transmit is disabled.
1: Transmit is enabled.
17SSC_RXENA
AT91C_SSC_RXENA
Receive Enable
0: Receive is disabled.
1: Receive is enabled.

SSC: AT91_REG SSC_IER - Interrupt Enable Register

Offset Name Description
0SSC_TXRDY
AT91C_SSC_TXRDY
Transmit Ready
0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1: SSC_THR is empty.
1SSC_TXEMPTY
AT91C_SSC_TXEMPTY
Transmit Empty
0: Data remains in SSC_THR or is currently transmitted from TSR.
1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
2SSC_ENDTX
AT91C_SSC_ENDTX
End Of Transmission
0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
3SSC_TXBUFE
AT91C_SSC_TXBUFE
Transmit Buffer Empty
0: SSC_TCR or SSC_TNCR have a value other than 0.
1: Both SSC_TCR and SSC_TNCR have a value of 0.
4SSC_RXRDY
AT91C_SSC_RXRDY
Receive Ready
0: SSC_RHR is empty.
1: Data has been received and loaded in SSC_RHR.
5SSC_OVRUN
AT91C_SSC_OVRUN
Receive Overrun
0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.
1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
6SSC_ENDRX
AT91C_SSC_ENDRX
End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
1: End of PDC transfer when Receive Counter Register has arrived at zero.
7SSC_RXBUFF
AT91C_SSC_RXBUFF
Receive Buffer Full
0: SSC_RCR or SSC_RNCR have a value other than 0.
1: Both SSC_RCR and SSC_RNCR have a value of 0.
8SSC_CP0
AT91C_SSC_CP0
Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
9SSC_CP1
AT91C_SSC_CP1
Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
10SSC_TXSYN
AT91C_SSC_TXSYN
Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
11SSC_RXSYN
AT91C_SSC_RXSYN
Receive Sync
0: A Rx Sync has not occurred since the last read of the Status Register.
1: A Rx Sync has occurred since the last read of the Status Register.

SSC: AT91_REG SSC_IDR - Interrupt Disable Register

Offset Name Description
0SSC_TXRDY
AT91C_SSC_TXRDY
Transmit Ready
0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1: SSC_THR is empty.
1SSC_TXEMPTY
AT91C_SSC_TXEMPTY
Transmit Empty
0: Data remains in SSC_THR or is currently transmitted from TSR.
1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
2SSC_ENDTX
AT91C_SSC_ENDTX
End Of Transmission
0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
3SSC_TXBUFE
AT91C_SSC_TXBUFE
Transmit Buffer Empty
0: SSC_TCR or SSC_TNCR have a value other than 0.
1: Both SSC_TCR and SSC_TNCR have a value of 0.
4SSC_RXRDY
AT91C_SSC_RXRDY
Receive Ready
0: SSC_RHR is empty.
1: Data has been received and loaded in SSC_RHR.
5SSC_OVRUN
AT91C_SSC_OVRUN
Receive Overrun
0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.
1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
6SSC_ENDRX
AT91C_SSC_ENDRX
End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
1: End of PDC transfer when Receive Counter Register has arrived at zero.
7SSC_RXBUFF
AT91C_SSC_RXBUFF
Receive Buffer Full
0: SSC_RCR or SSC_RNCR have a value other than 0.
1: Both SSC_RCR and SSC_RNCR have a value of 0.
8SSC_CP0
AT91C_SSC_CP0
Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
9SSC_CP1
AT91C_SSC_CP1
Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
10SSC_TXSYN
AT91C_SSC_TXSYN
Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
11SSC_RXSYN
AT91C_SSC_RXSYN
Receive Sync
0: A Rx Sync has not occurred since the last read of the Status Register.
1: A Rx Sync has occurred since the last read of the Status Register.

SSC: AT91_REG SSC_IMR - Interrupt Mask Register

Offset Name Description
0SSC_TXRDY
AT91C_SSC_TXRDY
Transmit Ready
0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1: SSC_THR is empty.
1SSC_TXEMPTY
AT91C_SSC_TXEMPTY
Transmit Empty
0: Data remains in SSC_THR or is currently transmitted from TSR.
1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
2SSC_ENDTX
AT91C_SSC_ENDTX
End Of Transmission
0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
3SSC_TXBUFE
AT91C_SSC_TXBUFE
Transmit Buffer Empty
0: SSC_TCR or SSC_TNCR have a value other than 0.
1: Both SSC_TCR and SSC_TNCR have a value of 0.
4SSC_RXRDY
AT91C_SSC_RXRDY
Receive Ready
0: SSC_RHR is empty.
1: Data has been received and loaded in SSC_RHR.
5SSC_OVRUN
AT91C_SSC_OVRUN
Receive Overrun
0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.
1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
6SSC_ENDRX
AT91C_SSC_ENDRX
End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
1: End of PDC transfer when Receive Counter Register has arrived at zero.
7SSC_RXBUFF
AT91C_SSC_RXBUFF
Receive Buffer Full
0: SSC_RCR or SSC_RNCR have a value other than 0.
1: Both SSC_RCR and SSC_RNCR have a value of 0.
8SSC_CP0
AT91C_SSC_CP0
Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
9SSC_CP1
AT91C_SSC_CP1
Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
10SSC_TXSYN
AT91C_SSC_TXSYN
Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
11SSC_RXSYN
AT91C_SSC_RXSYN
Receive Sync
0: A Rx Sync has not occurred since the last read of the Status Register.
1: A Rx Sync has occurred since the last read of the Status Register.

SSC: AT91S_PDC SSC - PDC interface