Timer Counter Channel Interface Peripheral

TC2 (AT91S_TC) 0xFFFA0080 (AT91C_BASE_TC2)
Periph ID AIC Symbol Description
14 (AT91C_ID_TC2) Timer Counter 2

Signal Symbol PIO controller Description
TIOA2(AT91C_PA26_TIOA2 )PIOA Periph: B Bit: 26Timer Counter 2 Multipurpose Timer I/O Pin A
TIOB2(AT91C_PA27_TIOB2 )PIOA Periph: B Bit: 27Timer Counter 2 Multipurpose Timer I/O Pin B
TCLK2(AT91C_PA29_TCLK2 )PIOA Periph: B Bit: 29Timer Counter 2 external clock input

Function Description
AT91F_TC2_CfgPIOConfigure PIO controllers to drive TC2 signals
AT91F_TC2_CfgPMCEnable Peripheral clock in PMC for TC2


TC1 (AT91S_TC) 0xFFFA0040 (AT91C_BASE_TC1)
Periph ID AIC Symbol Description
13 (AT91C_ID_TC1)Timer Counter 1

Signal Symbol PIO controller Description
TIOA1(AT91C_PA15_TIOA1 )PIOA Periph: B Bit: 15Timer Counter 1 Multipurpose Timer I/O Pin A
TIOB1(AT91C_PA16_TIOB1 )PIOA Periph: B Bit: 16Timer Counter 1 Multipurpose Timer I/O Pin B
TCLK1(AT91C_PA28_TCLK1 )PIOA Periph: B Bit: 28Timer Counter 1 external clock input

Function Description
AT91F_TC1_CfgPIOConfigure PIO controllers to drive TC1 signals
AT91F_TC1_CfgPMCEnable Peripheral clock in PMC for TC1


TC0 (AT91S_TC) 0xFFFA0000 (AT91C_BASE_TC0)
Periph ID AIC Symbol Description
12 (AT91C_ID_TC0)Timer Counter 0

Signal Symbol PIO controller Description
TIOA0(AT91C_PA0_TIOA0 )PIOA Periph: B Bit: 0Timer Counter 0 Multipurpose Timer I/O Pin A
TIOB0(AT91C_PA1_TIOB0 )PIOA Periph: B Bit: 1Timer Counter 0 Multipurpose Timer I/O Pin B
TCLK0(AT91C_PA4_TCLK0 )PIOA Periph: B Bit: 4Timer Counter 0 external clock input

Function Description
AT91F_TC0_CfgPIOConfigure PIO controllers to drive TC0 signals
AT91F_TC0_CfgPMCEnable Peripheral clock in PMC for TC0


TC Software API (AT91S_TC)

Offset Field Description
0x0TC_CCRChannel Control Register
0x4TC_CMRChannel Mode Register (Capture Mode / Waveform Mode)
0x10TC_CVCounter Value
0x14TC_RARegister A
0x18TC_RBRegister B
0x1CTC_RCRegister C
0x20TC_SRStatus Register
0x24TC_IERInterrupt Enable Register
0x28TC_IDRInterrupt Disable Register
0x2CTC_IMRInterrupt Mask Register

Function Description
AT91F_TC_GetInterruptMaskStatusReturn TC Interrupt Mask Status
AT91F_TC_IsInterruptMaskedTest if TC Interrupt is Masked
AT91F_TC_InterruptDisableDisable TC Interrupt
AT91F_TC_InterruptEnableEnable TC Interrupt

TC Register Description

TC: AT91_REG TC_CCR - Channel Control Register

Offset Name Description
0TC_CLKEN
AT91C_TC_CLKEN
Counter Clock Enable Command
0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
1TC_CLKDIS
AT91C_TC_CLKDIS
Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
2TC_SWTRG
AT91C_TC_SWTRG
Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and clock is started.

TC: AT91_REG TC_CMR - Channel Mode Register (Capture Mode / Waveform Mode)

Offset Name Description
2..0TC_CLKS
AT91C_TC_CLKS
Clock Selection
ValueLabelDescription
0TC_CLKS_TIMER_DIV1_CLOCK
AT91C_TC_CLKS_TIMER_DIV1_CLOCK

Clock selected: TIMER_DIV1_CLOCK
1TC_CLKS_TIMER_DIV2_CLOCK
AT91C_TC_CLKS_TIMER_DIV2_CLOCK

Clock selected: TIMER_DIV2_CLOCK
2TC_CLKS_TIMER_DIV3_CLOCK
AT91C_TC_CLKS_TIMER_DIV3_CLOCK

Clock selected: TIMER_DIV3_CLOCK
3TC_CLKS_TIMER_DIV4_CLOCK
AT91C_TC_CLKS_TIMER_DIV4_CLOCK

Clock selected: TIMER_DIV4_CLOCK
4TC_CLKS_TIMER_DIV5_CLOCK
AT91C_TC_CLKS_TIMER_DIV5_CLOCK

Clock selected: TIMER_DIV5_CLOCK
5TC_CLKS_XC0
AT91C_TC_CLKS_XC0

Clock selected: XC0
6TC_CLKS_XC1
AT91C_TC_CLKS_XC1

Clock selected: XC1
7TC_CLKS_XC2
AT91C_TC_CLKS_XC2

Clock selected: XC2
3aTC_CLKI
AT91C_TC_CLKI
Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
5..4TC_BURST
AT91C_TC_BURST
Burst Signal Selection
ValueLabelDescription
0TC_BURST_NONE
AT91C_TC_BURST_NONE

The clock is not gated by an external signal
1TC_BURST_XC0
AT91C_TC_BURST_XC0

XC0 is ANDed with the selected clock
2TC_BURST_XC1
AT91C_TC_BURST_XC1

XC1 is ANDed with the selected clock
3TC_BURST_XC2
AT91C_TC_BURST_XC2

XC2 is ANDed with the selected clock
6aTC_LDBSTOP
AT91C_TC_LDBSTOP
Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
7aTC_LDBDIS
AT91C_TC_LDBDIS
Counter Clock Disabled with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
9..8TC_ETRGEDG
AT91C_TC_ETRGEDG
External Trigger Edge Selection
ValueLabelDescription
0TC_ETRGEDG_NONE
AT91C_TC_ETRGEDG_NONE

Edge: None
1TC_ETRGEDG_RISING
AT91C_TC_ETRGEDG_RISING

Edge: rising edge
2TC_ETRGEDG_FALLING
AT91C_TC_ETRGEDG_FALLING

Edge: falling edge
3TC_ETRGEDG_BOTH
AT91C_TC_ETRGEDG_BOTH

Edge: each edge
10aTC_ABETRG
AT91C_TC_ABETRG
TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
14aTC_CPCTRG
AT91C_TC_CPCTRG
RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
15aTC_WAVE
AT91C_TC_WAVE

0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
17..16TC_LDRA
AT91C_TC_LDRA
RA Loading Selection
ValueLabelDescription
0TC_LDRA_NONE
AT91C_TC_LDRA_NONE

Edge: None
1TC_LDRA_RISING
AT91C_TC_LDRA_RISING

Edge: rising edge of TIOA
2TC_LDRA_FALLING
AT91C_TC_LDRA_FALLING

Edge: falling edge of TIOA
3TC_LDRA_BOTH
AT91C_TC_LDRA_BOTH

Edge: each edge of TIOA
19..18TC_LDRB
AT91C_TC_LDRB
RB Loading Selection
ValueLabelDescription
0TC_LDRB_NONE
AT91C_TC_LDRB_NONE

Edge: None
1TC_LDRB_RISING
AT91C_TC_LDRB_RISING

Edge: rising edge of TIOA
2TC_LDRB_FALLING
AT91C_TC_LDRB_FALLING

Edge: falling edge of TIOA
3TC_LDRB_BOTH
AT91C_TC_LDRB_BOTH

Edge: each edge of TIOA
2..0TC_CLKS
AT91C_TC_CLKS
Clock Selection
ValueLabelDescription
0TC_CLKS_TIMER_DIV1_CLOCK
AT91C_TC_CLKS_TIMER_DIV1_CLOCK

Clock selected: TIMER_DIV1_CLOCK
1TC_CLKS_TIMER_DIV2_CLOCK
AT91C_TC_CLKS_TIMER_DIV2_CLOCK

Clock selected: TIMER_DIV2_CLOCK
2TC_CLKS_TIMER_DIV3_CLOCK
AT91C_TC_CLKS_TIMER_DIV3_CLOCK

Clock selected: TIMER_DIV3_CLOCK
3TC_CLKS_TIMER_DIV4_CLOCK
AT91C_TC_CLKS_TIMER_DIV4_CLOCK

Clock selected: TIMER_DIV4_CLOCK
4TC_CLKS_TIMER_DIV5_CLOCK
AT91C_TC_CLKS_TIMER_DIV5_CLOCK

Clock selected: TIMER_DIV5_CLOCK
5TC_CLKS_XC0
AT91C_TC_CLKS_XC0

Clock selected: XC0
6TC_CLKS_XC1
AT91C_TC_CLKS_XC1

Clock selected: XC1
7TC_CLKS_XC2
AT91C_TC_CLKS_XC2

Clock selected: XC2
3bTC_CLKI
AT91C_TC_CLKI
Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
5..4TC_BURST
AT91C_TC_BURST
Burst Signal Selection
ValueLabelDescription
0TC_BURST_NONE
AT91C_TC_BURST_NONE

The clock is not gated by an external signal
1TC_BURST_XC0
AT91C_TC_BURST_XC0

XC0 is ANDed with the selected clock
2TC_BURST_XC1
AT91C_TC_BURST_XC1

XC1 is ANDed with the selected clock
3TC_BURST_XC2
AT91C_TC_BURST_XC2

XC2 is ANDed with the selected clock
6bTC_CPCSTOP
AT91C_TC_CPCSTOP
Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
7bTC_CPCDIS
AT91C_TC_CPCDIS
Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
9..8TC_EEVTEDG
AT91C_TC_EEVTEDG
External Event Edge Selection
ValueLabelDescription
0TC_EEVTEDG_NONE
AT91C_TC_EEVTEDG_NONE

Edge: None
1TC_EEVTEDG_RISING
AT91C_TC_EEVTEDG_RISING

Edge: rising edge
2TC_EEVTEDG_FALLING
AT91C_TC_EEVTEDG_FALLING

Edge: falling edge
3TC_EEVTEDG_BOTH
AT91C_TC_EEVTEDG_BOTH

Edge: each edge
11..10TC_EEVT
AT91C_TC_EEVT
External Event Selection
ValueLabelDescription
0TC_EEVT_NONE
AT91C_TC_EEVT_NONE

Signal selected as external event: TIOB TIOB direction: input
1TC_EEVT_RISING
AT91C_TC_EEVT_RISING

Signal selected as external event: XC0 TIOB direction: output
2TC_EEVT_FALLING
AT91C_TC_EEVT_FALLING

Signal selected as external event: XC1 TIOB direction: output
3TC_EEVT_BOTH
AT91C_TC_EEVT_BOTH

Signal selected as external event: XC2 TIOB direction: output
12bTC_ENETRG
AT91C_TC_ENETRG
External Event Trigger enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
1 = The external event resets the counter and starts the counter clock.
14..13TC_WAVESEL
AT91C_TC_WAVESEL
Waveform Selection
ValueLabelDescription
0TC_WAVESEL_UP
AT91C_TC_WAVESEL_UP

UP mode without atomatic trigger on RC Compare
1TC_WAVESEL_UPDOWN
AT91C_TC_WAVESEL_UPDOWN

UPDOWN mode without automatic trigger on RC Compare
2TC_WAVESEL_UP_AUTO
AT91C_TC_WAVESEL_UP_AUTO

UP mode with automatic trigger on RC Compare
3TC_WAVESEL_UPDOWN_AUTO
AT91C_TC_WAVESEL_UPDOWN_AUTO

UPDOWN mode with automatic trigger on RC Compare
15bTC_WAVE
AT91C_TC_WAVE

0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
17..16TC_ACPA
AT91C_TC_ACPA
RA Compare Effect on TIOA
ValueLabelDescription
0TC_ACPA_NONE
AT91C_TC_ACPA_NONE

Effect: none
1TC_ACPA_SET
AT91C_TC_ACPA_SET

Effect: set
2TC_ACPA_CLEAR
AT91C_TC_ACPA_CLEAR

Effect: clear
3TC_ACPA_TOGGLE
AT91C_TC_ACPA_TOGGLE

Effect: toggle
19..18TC_ACPC
AT91C_TC_ACPC
RC Compare Effect on TIOA
ValueLabelDescription
0TC_ACPC_NONE
AT91C_TC_ACPC_NONE

Effect: none
1TC_ACPC_SET
AT91C_TC_ACPC_SET

Effect: set
2TC_ACPC_CLEAR
AT91C_TC_ACPC_CLEAR

Effect: clear
3TC_ACPC_TOGGLE
AT91C_TC_ACPC_TOGGLE

Effect: toggle
21..20TC_AEEVT
AT91C_TC_AEEVT
External Event Effect on TIOA
ValueLabelDescription
0TC_AEEVT_NONE
AT91C_TC_AEEVT_NONE

Effect: none
1TC_AEEVT_SET
AT91C_TC_AEEVT_SET

Effect: set
2TC_AEEVT_CLEAR
AT91C_TC_AEEVT_CLEAR

Effect: clear
3TC_AEEVT_TOGGLE
AT91C_TC_AEEVT_TOGGLE

Effect: toggle
23..22TC_ASWTRG
AT91C_TC_ASWTRG
Software Trigger Effect on TIOA
ValueLabelDescription
0TC_ASWTRG_NONE
AT91C_TC_ASWTRG_NONE

Effect: none
1TC_ASWTRG_SET
AT91C_TC_ASWTRG_SET

Effect: set
2TC_ASWTRG_CLEAR
AT91C_TC_ASWTRG_CLEAR

Effect: clear
3TC_ASWTRG_TOGGLE
AT91C_TC_ASWTRG_TOGGLE

Effect: toggle
25..24TC_BCPB
AT91C_TC_BCPB
RB Compare Effect on TIOB
ValueLabelDescription
0TC_BCPB_NONE
AT91C_TC_BCPB_NONE

Effect: none
1TC_BCPB_SET
AT91C_TC_BCPB_SET

Effect: set
2TC_BCPB_CLEAR
AT91C_TC_BCPB_CLEAR

Effect: clear
3TC_BCPB_TOGGLE
AT91C_TC_BCPB_TOGGLE

Effect: toggle
27..26TC_BCPC
AT91C_TC_BCPC
RC Compare Effect on TIOB
ValueLabelDescription
0TC_BCPC_NONE
AT91C_TC_BCPC_NONE

Effect: none
1TC_BCPC_SET
AT91C_TC_BCPC_SET

Effect: set
2TC_BCPC_CLEAR
AT91C_TC_BCPC_CLEAR

Effect: clear
3TC_BCPC_TOGGLE
AT91C_TC_BCPC_TOGGLE

Effect: toggle
29..28TC_BEEVT
AT91C_TC_BEEVT
External Event Effect on TIOB
ValueLabelDescription
0TC_BEEVT_NONE
AT91C_TC_BEEVT_NONE

Effect: none
1TC_BEEVT_SET
AT91C_TC_BEEVT_SET

Effect: set
2TC_BEEVT_CLEAR
AT91C_TC_BEEVT_CLEAR

Effect: clear
3TC_BEEVT_TOGGLE
AT91C_TC_BEEVT_TOGGLE

Effect: toggle
31..30TC_BSWTRG
AT91C_TC_BSWTRG
Software Trigger Effect on TIOB
ValueLabelDescription
0TC_BSWTRG_NONE
AT91C_TC_BSWTRG_NONE

Effect: none
1TC_BSWTRG_SET
AT91C_TC_BSWTRG_SET

Effect: set
2TC_BSWTRG_CLEAR
AT91C_TC_BSWTRG_CLEAR

Effect: clear
3TC_BSWTRG_TOGGLE
AT91C_TC_BSWTRG_TOGGLE

Effect: toggle

TC: AT91_REG TC_CV - Counter Value


0-65535 Counter Value contains the counter value in real time.

TC: AT91_REG TC_RA - Register A


TC Register A contains the Register A value in real time

TC: AT91_REG TC_RB - Register B


TC Register B contains the Register B value in real time

TC: AT91_REG TC_RC - Register C


TC Register C contains the Register C value in real time

TC: AT91_REG TC_SR - Status Register

Offset Name Description
0TC_COVFS
AT91C_TC_COVFS
Counter Overflow
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
1TC_LOVRS
AT91C_TC_LOVRS
Load Overrun
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2TC_CPAS
AT91C_TC_CPAS
RA Compare
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3TC_CPBS
AT91C_TC_CPBS
RB Compare
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4TC_CPCS
AT91C_TC_CPCS
RC Compare
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
5TC_LDRAS
AT91C_TC_LDRAS
RA Loading
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6TC_LDRBS
AT91C_TC_LDRBS
RB Loading
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7TC_ETRCS
AT91C_TC_ETRCS
External Trigger
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
16TC_ETRGS
AT91C_TC_ETRGS
Clock Enabling
0 = Clock is disabled.
1 = Clock is enabled.
17TC_MTIOA
AT91C_TC_MTIOA
TIOA Mirror
0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
18TC_MTIOB
AT91C_TC_MTIOB
TIOA Mirror
0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

TC: AT91_REG TC_IER - Interrupt Enable Register

Offset Name Description
0TC_COVFS
AT91C_TC_COVFS
Counter Overflow
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
1TC_LOVRS
AT91C_TC_LOVRS
Load Overrun
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2TC_CPAS
AT91C_TC_CPAS
RA Compare
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3TC_CPBS
AT91C_TC_CPBS
RB Compare
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4TC_CPCS
AT91C_TC_CPCS
RC Compare
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
5TC_LDRAS
AT91C_TC_LDRAS
RA Loading
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6TC_LDRBS
AT91C_TC_LDRBS
RB Loading
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7TC_ETRCS
AT91C_TC_ETRCS
External Trigger
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.

TC: AT91_REG TC_IDR - Interrupt Disable Register

Offset Name Description
0TC_COVFS
AT91C_TC_COVFS
Counter Overflow
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
1TC_LOVRS
AT91C_TC_LOVRS
Load Overrun
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2TC_CPAS
AT91C_TC_CPAS
RA Compare
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3TC_CPBS
AT91C_TC_CPBS
RB Compare
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4TC_CPCS
AT91C_TC_CPCS
RC Compare
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
5TC_LDRAS
AT91C_TC_LDRAS
RA Loading
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6TC_LDRBS
AT91C_TC_LDRBS
RB Loading
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7TC_ETRCS
AT91C_TC_ETRCS
External Trigger
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.

TC: AT91_REG TC_IMR - Interrupt Mask Register

Offset Name Description
0TC_COVFS
AT91C_TC_COVFS
Counter Overflow
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
1TC_LOVRS
AT91C_TC_LOVRS
Load Overrun
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-tus Register, if WAVE = 0.
2TC_CPAS
AT91C_TC_CPAS
RA Compare
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
3TC_CPBS
AT91C_TC_CPBS
RB Compare
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
4TC_CPCS
AT91C_TC_CPCS
RC Compare
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
5TC_LDRAS
AT91C_TC_LDRAS
RA Loading
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
6TC_LDRBS
AT91C_TC_LDRBS
RB Loading
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
7TC_ETRCS
AT91C_TC_ETRCS
External Trigger
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.