Two-wire Interface Peripheral

TWI (AT91S_TWI) 0xFFFB8000 (AT91C_BASE_TWI)
Periph ID AIC Symbol Description
9 (AT91C_ID_TWI)Two-Wire Interface

Signal Symbol PIO controller Description
TWD(AT91C_PA3_TWD )PIOA Periph: A Bit: 3TWI Two-wire Serial Data
TWCK(AT91C_PA4_TWCK )PIOA Periph: A Bit: 4TWI Two-wire Serial Clock

Function Description
AT91F_TWI_CfgPIOConfigure PIO controllers to drive TWI signals
AT91F_TWI_CfgPMCEnable Peripheral clock in PMC for TWI


TWI Software API (AT91S_TWI)

Offset Field Description
0x0TWI_CRControl Register
0x4TWI_MMRMaster Mode Register
0x8TWI_SMRSlave Mode Register
0xCTWI_IADRInternal Address Register
0x10TWI_CWGRClock Waveform Generator Register
0x20TWI_SRStatus Register
0x24TWI_IERInterrupt Enable Register
0x28TWI_IDRInterrupt Disable Register
0x2CTWI_IMRInterrupt Mask Register
0x30TWI_RHRReceive Holding Register
0x34TWI_THRTransmit Holding Register

Function Description
AT91F_TWI_EnableItEnable TWI IT
AT91F_TWI_DisableItDisable TWI IT
AT91F_TWI_GetInterruptMaskStatusReturn TWI Interrupt Mask Status
AT91F_TWI_IsInterruptMaskedTest if TWI Interrupt is Masked
AT91F_TWI_ConfigureConfigure TWI in master mode

TWI Register Description

TWI: AT91_REG TWI_CR - Control Register

Offset Name Description
0TWI_START
AT91C_TWI_START
Send a START Condition
0: No effect.
1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register.
1TWI_STOP
AT91C_TWI_STOP
Send a STOP Condition
0: No effect.
1: STOP Condition is sent just after completing the current byte transmission in master read or write mode.
In single data byte master read or write, the START and STOP must both be set.
In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission.
In master read mode, if a NACK bit is received, the STOP is automatically performed.
In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.
2TWI_MSEN
AT91C_TWI_MSEN
TWI Master Transfer Enabled
0: No effect.
1: If MSDIS = 0, the master data transfer is enabled.
3TWI_MSDIS
AT91C_TWI_MSDIS
TWI Master Transfer Disabled
0: No effect.
1: The master data transfer is disabled, all pending data is transmitted. The shifter and holding character (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.
4TWI_SVEN
AT91C_TWI_SVEN
TWI Slave Transfer Enabled
0: No effect.
1: If SVDIS = 0, the slave data transfer is enabled.
5TWI_SVDIS
AT91C_TWI_SVDIS
TWI Slave Transfer Disabled
0: No effect.
1: The slave data transfer is disabled.
7TWI_SWRST
AT91C_TWI_SWRST
Software Reset
0: No effect.
1: Equivalent to a system reset.

TWI: AT91_REG TWI_MMR - Master Mode Register

Offset Name Description
9..8TWI_IADRSZ
AT91C_TWI_IADRSZ
Internal Device Address Size
ValueLabelDescription
0TWI_IADRSZ_NO
AT91C_TWI_IADRSZ_NO

No internal device address
1TWI_IADRSZ_1_BYTE
AT91C_TWI_IADRSZ_1_BYTE

One-byte internal device address
2TWI_IADRSZ_2_BYTE
AT91C_TWI_IADRSZ_2_BYTE

Two-byte internal device address
3TWI_IADRSZ_3_BYTE
AT91C_TWI_IADRSZ_3_BYTE

Three-byte internal device address
12TWI_MREAD
AT91C_TWI_MREAD
Master Read Direction
0: Master write direction
1: Master read direction
22..16TWI_DADR
AT91C_TWI_DADR
Device Address
The device address is used in master mode to access slave devices in read or write mode.

TWI: AT91_REG TWI_SMR - Slave Mode Register

Offset Name Description
22..16TWI_SADR
AT91C_TWI_SADR
Slave Device Address
The slave device address is used in slave mode in order to be accessed by master devices in read or write mode.

TWI: AT91_REG TWI_IADR - Internal Address Register


0, 1, 2 or 3 bytes depending on IADRSZ

TWI: AT91_REG TWI_CWGR - Clock Waveform Generator Register

Offset Name Description
7..0TWI_CLDIV
AT91C_TWI_CLDIV
Clock Low Divider
The SCL low period is defined as follows: Tlow = (CLDIV * 2 ^CKDIV) + 4) * Tmclk
15..8TWI_CHDIV
AT91C_TWI_CHDIV
Clock High Divider
The SCL high period is defined as follows: Thigh = (CLDIV * 2 ^CKDIV) + 4) * Tmclk
18..16TWI_CKDIV
AT91C_TWI_CKDIV
Clock Divider
The CKDIV is used to increase both SCL high and low periods.

TWI: AT91_REG TWI_SR - Status Register

Offset Name Description
0TWI_TXCOMP
AT91C_TWI_TXCOMP
Transmission Completed
0: In master, during the length of the current frame. In slave, from START received to STOP received.
1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).
1TWI_RXRDY
AT91C_TWI_RXRDY
Receive holding register ReaDY
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in theTWI_RHR since the last read.
2TWI_TXRDY
AT91C_TWI_TXRDY
Transmit holding register ReaDY
0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
3TWI_SVREAD
AT91C_TWI_SVREAD
Slave Read
0: Slave accessed in write direction, valid only if SVACC is set.
1: Slave accessed in read direction, valid only if SVACC is set.
4TWI_SVACC
AT91C_TWI_SVACC
Slave Access
0: No slave access
1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.
5TWI_GCACC
AT91C_TWI_GCACC
General Call Access
0: No slave access
1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.
6TWI_OVRE
AT91C_TWI_OVRE
Overrun Error
0: TWI_RHR has not been loaded while RXRDY was set
1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
7TWI_UNRE
AT91C_TWI_UNRE
Underrun Error
0: No underrun error
1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.
8TWI_NACK
AT91C_TWI_NACK
Not Acknowledged
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
9TWI_ARBLST
AT91C_TWI_ARBLST
Arbitration Lost
0: Arbitration win
1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.

TWI: AT91_REG TWI_IER - Interrupt Enable Register

Offset Name Description
0TWI_TXCOMP
AT91C_TWI_TXCOMP
Transmission Completed
0: In master, during the length of the current frame. In slave, from START received to STOP received.
1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).
1TWI_RXRDY
AT91C_TWI_RXRDY
Receive holding register ReaDY
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in theTWI_RHR since the last read.
2TWI_TXRDY
AT91C_TWI_TXRDY
Transmit holding register ReaDY
0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
3TWI_SVREAD
AT91C_TWI_SVREAD
Slave Read
0: Slave accessed in write direction, valid only if SVACC is set.
1: Slave accessed in read direction, valid only if SVACC is set.
4TWI_SVACC
AT91C_TWI_SVACC
Slave Access
0: No slave access
1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.
5TWI_GCACC
AT91C_TWI_GCACC
General Call Access
0: No slave access
1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.
6TWI_OVRE
AT91C_TWI_OVRE
Overrun Error
0: TWI_RHR has not been loaded while RXRDY was set
1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
7TWI_UNRE
AT91C_TWI_UNRE
Underrun Error
0: No underrun error
1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.
8TWI_NACK
AT91C_TWI_NACK
Not Acknowledged
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
9TWI_ARBLST
AT91C_TWI_ARBLST
Arbitration Lost
0: Arbitration win
1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.

TWI: AT91_REG TWI_IDR - Interrupt Disable Register

Offset Name Description
0TWI_TXCOMP
AT91C_TWI_TXCOMP
Transmission Completed
0: In master, during the length of the current frame. In slave, from START received to STOP received.
1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).
1TWI_RXRDY
AT91C_TWI_RXRDY
Receive holding register ReaDY
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in theTWI_RHR since the last read.
2TWI_TXRDY
AT91C_TWI_TXRDY
Transmit holding register ReaDY
0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
3TWI_SVREAD
AT91C_TWI_SVREAD
Slave Read
0: Slave accessed in write direction, valid only if SVACC is set.
1: Slave accessed in read direction, valid only if SVACC is set.
4TWI_SVACC
AT91C_TWI_SVACC
Slave Access
0: No slave access
1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.
5TWI_GCACC
AT91C_TWI_GCACC
General Call Access
0: No slave access
1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.
6TWI_OVRE
AT91C_TWI_OVRE
Overrun Error
0: TWI_RHR has not been loaded while RXRDY was set
1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
7TWI_UNRE
AT91C_TWI_UNRE
Underrun Error
0: No underrun error
1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.
8TWI_NACK
AT91C_TWI_NACK
Not Acknowledged
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
9TWI_ARBLST
AT91C_TWI_ARBLST
Arbitration Lost
0: Arbitration win
1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.

TWI: AT91_REG TWI_IMR - Interrupt Mask Register

Offset Name Description
0TWI_TXCOMP
AT91C_TWI_TXCOMP
Transmission Completed
0: In master, during the length of the current frame. In slave, from START received to STOP received.
1: When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI).
1TWI_RXRDY
AT91C_TWI_RXRDY
Receive holding register ReaDY
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in theTWI_RHR since the last read.
2TWI_TXRDY
AT91C_TWI_TXRDY
Transmit holding register ReaDY
0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
3TWI_SVREAD
AT91C_TWI_SVREAD
Slave Read
0: Slave accessed in write direction, valid only if SVACC is set.
1: Slave accessed in read direction, valid only if SVACC is set.
4TWI_SVACC
AT91C_TWI_SVACC
Slave Access
0: No slave access
1: The device address received matches the SADR register. Reset by read in TWI_SR when TXCOMP is set.
5TWI_GCACC
AT91C_TWI_GCACC
General Call Access
0: No slave access
1: The received device address matches the general call address. Reset by read in TWI_SR when TXCOMP is set.
6TWI_OVRE
AT91C_TWI_OVRE
Overrun Error
0: TWI_RHR has not been loaded while RXRDY was set
1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
7TWI_UNRE
AT91C_TWI_UNRE
Underrun Error
0: No underrun error
1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in master mode. Reset by read in TWI_SR when TXCOMP is set.
8TWI_NACK
AT91C_TWI_NACK
Not Acknowledged
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
9TWI_ARBLST
AT91C_TWI_ARBLST
Arbitration Lost
0: Arbitration win
1: Arbitration lost; another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. Reset by read in TWI_SR.

TWI: AT91_REG TWI_RHR - Receive Holding Register


Master or Slave Receive Holding Data

TWI: AT91_REG TWI_THR - Transmit Holding Register


Master or Slave Transmit Holding Data