USB Device Interface Peripheral

UDP (AT91S_UDP) 0xFFFB0000 (AT91C_BASE_UDP)
Periph ID AIC Symbol Description
11 (AT91C_ID_UDP)USB Device Port

Function Description
AT91F_UDP_CfgPMCEnable Peripheral clock in PMC for UDP


UDP Software API (AT91S_UDP)

Offset Field Description
0x0UDP_NUM (UDP_FRM_NUM)Frame Number Register
0x4UDP_GLBSTATE (UDP_GLB_STATE)Global State Register
0x8UDP_FADDRFunction Address Register
0x10UDP_IERInterrupt Enable Register
0x14UDP_IDRInterrupt Disable Register
0x18UDP_IMRInterrupt Mask Register
0x1CUDP_ISRInterrupt Status Register
0x20UDP_ICRInterrupt Clear Register
0x28UDP_RSTEP (UDP_RST_EP)Reset Endpoint Register
0x30UDP_CSR[8] (UDP_CSR)Endpoint Control and Status Register
0x50UDP_FDR[8] (UDP_FDR)Endpoint FIFO Data Register

Function Description
AT91F_UDP_EpClearClear flag in the endpoint CSR register
AT91F_UDP_ResetEpReset UDP endpoint
AT91F_UDP_EpWriteWrite value in the DPR
AT91F_UDP_EnableItEnable UDP IT
AT91F_UDP_EpSetSet flag in the endpoint CSR register
AT91F_UDP_DisableEpEnable Endpoint
AT91F_UDP_EpStallEndpoint will STALL requests
AT91F_UDP_EpReadReturn value from the DPR
AT91F_UDP_SetAddressSet UDP functional address
AT91F_UDP_EpStatusReturn the endpoint CSR register
AT91F_UDP_IsInterruptMaskedTest if UDP Interrupt is Masked
AT91F_UDP_GetInterruptMaskStatusReturn UDP Interrupt Mask Status
AT91F_UDP_GetStatereturn UDP Device state
AT91F_UDP_SetStateSet UDP Device state
AT91F_UDP_EnableEpEnable Endpoint
AT91F_UDP_EpEndOfWrNotify the UDP that values in DPR are ready to be sent
AT91F_UDP_DisableItDisable UDP IT

UDP Register Description

UDP: AT91_REG UDP_FRM_NUM - Frame Number Register

Offset Name Description
10..0UDP_FRM_NUM
AT91C_UDP_FRM_NUM
Frame Number as Defined in the Packet Field Formats
This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP(Start of Frame End of Packet).
16UDP_FRM_ERR
AT91C_UDP_FRM_ERR
Frame Error
This bit is set at SOF_EOP when the SOF packet is received containing an error.
This bit is reset upon receipt of SOF_PID.
17UDP_FRM_OK
AT91C_UDP_FRM_OK
Frame OK
This bit is set at SOF_EOP when the SOF packet is received without any error.
This bit is reset upon receipt of SOF_PID (Packet Identification).
In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP.
Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.

UDP: AT91_REG UDP_GLBSTATE - Global State Register

Offset Name Description
0UDP_FADDEN
AT91C_UDP_FADDEN
Function Address Enable
Read:
0 = Device is not in address state.
1 = Device is in address state.
Write:
0 = No effect, only a reset can bring back a device to the default state.
1 = Set device in address state. This occurs after a successful Set Address request. Beforehand, the USB_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FAD-DEN. Please refer to chapter 9 of the Universal Serial Bus Specification, Rev. 1.1 to get more details.
1UDP_CONFG
AT91C_UDP_CONFG
Configured
Read:
0 = Device is not in configured state.
1 = Device is in configured state.
Write:
0 = Set device in a nonconfigured state
1 = Set device in configured state.
The device is set in configured state when it is in address state and receives a successful Set Configuration request. Please refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 1.1 to get more details.
2UDP_RMWUPE
AT91C_UDP_RMWUPE
Remote Wake Up Enable
0 = Disable function's remote wake up.
1 = Enable function's remote wake up.
This bit is set if the function's remote wake up feature is enabled. When an asynchronous rising edge is detected on send_resume pin, if RMWUPE = 1, then a RESUME state is sent to the host.
3UDP_RSMINPR
AT91C_UDP_RSMINPR
A Resume Has Been Sent to the Host
Read:
0 = No effect.
1 = A Resume has been received from the host during Remote Wake Up feature.

UDP: AT91_REG UDP_FADDR - Function Address Register

Offset Name Description
7..0UDP_FADD
AT91C_UDP_FADD
Function Address Value
The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Please refer to the Universal Serial Bus Specifica-tion, Rev. 1.1 to get more information. After power up, or reset, the function address value is set to 0.
8UDP_FEN
AT91C_UDP_FEN
Function Enable
Read:
0 = Function endpoint disabled.
1 = Function endpoint enabled.
Write:
0 = Disable function endpoint.
1 = Default value.
The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller will set this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host.

UDP: AT91_REG UDP_IER - Interrupt Enable Register

Offset Name Description
0UDP_EPINT0
AT91C_UDP_EPINT0
Endpoint 0 Interrupt
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.
1UDP_EPINT1
AT91C_UDP_EPINT1
Endpoint 0 Interrupt
0 = No Endpoint1 Interrupt pending.
1 = Endpoint1 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.
2UDP_EPINT2
AT91C_UDP_EPINT2
Endpoint 2 Interrupt
0 = No Endpoint2 Interrupt pending.
1 = Endpoint2 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.
3UDP_EPINT3
AT91C_UDP_EPINT3
Endpoint 3 Interrupt
0 = No Endpoint3 Interrupt pending.
1 = Endpoint3 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR3:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit.
4UDP_EPINT4
AT91C_UDP_EPINT4
Endpoint 4 Interrupt
0 = No Endpoint4 Interrupt pending.
1 = Endpoint4 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR4:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit.
5UDP_EPINT5
AT91C_UDP_EPINT5
Endpoint 5 Interrupt
0 = No Endpoint5 Interrupt pending.
1 = Endpoint5 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR5:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit.
6UDP_EPINT6
AT91C_UDP_EPINT6
Endpoint 6 Interrupt
0 = No Endpoint6 Interrupt pending.
1 = Endpoint6 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR6:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP6INT is a sticky bit. Interrupt remains valid until EP6INT is cleared by writing in the corresponding USB_CSR6 bit.
7UDP_EPINT7
AT91C_UDP_EPINT7
Endpoint 7 Interrupt
0 = No Endpoint7 Interrupt pending.
1 = Endpoint7 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR7:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP7INT is a sticky bit. Interrupt remains valid until EP7INT is cleared by writing in the corresponding USB_CSR7 bit.
8UDP_RXSUSP
AT91C_UDP_RXSUSP
USB Suspend Interrupt
0 = No USB Suspend Interrupt pending.
1 = USB Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
9UDP_RXRSM
AT91C_UDP_RXRSM
USB Resume Interrupt
0 = No USB Resume Interrupt pending.
1 =USB Resume Interrupt has been raised.
The USB device sets this bit when a USB resume signal is detected at its port.
10UDP_EXTRSM
AT91C_UDP_EXTRSM
USB External Resume Interrupt
0 = No External Resume Interrupt pending.
1 = External Resume Interrupt has been raised.
This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.
11UDP_SOFINT
AT91C_UDP_SOFINT
USB Start Of frame Interrupt
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.
13UDP_WAKEUP
AT91C_UDP_WAKEUP
USB Resume Interrupt
0 = No Wakeup Interrupt pending.
1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.

UDP: AT91_REG UDP_IDR - Interrupt Disable Register

Offset Name Description
0UDP_EPINT0
AT91C_UDP_EPINT0
Endpoint 0 Interrupt
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.
1UDP_EPINT1
AT91C_UDP_EPINT1
Endpoint 0 Interrupt
0 = No Endpoint1 Interrupt pending.
1 = Endpoint1 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.
2UDP_EPINT2
AT91C_UDP_EPINT2
Endpoint 2 Interrupt
0 = No Endpoint2 Interrupt pending.
1 = Endpoint2 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.
3UDP_EPINT3
AT91C_UDP_EPINT3
Endpoint 3 Interrupt
0 = No Endpoint3 Interrupt pending.
1 = Endpoint3 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR3:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit.
4UDP_EPINT4
AT91C_UDP_EPINT4
Endpoint 4 Interrupt
0 = No Endpoint4 Interrupt pending.
1 = Endpoint4 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR4:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit.
5UDP_EPINT5
AT91C_UDP_EPINT5
Endpoint 5 Interrupt
0 = No Endpoint5 Interrupt pending.
1 = Endpoint5 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR5:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit.
6UDP_EPINT6
AT91C_UDP_EPINT6
Endpoint 6 Interrupt
0 = No Endpoint6 Interrupt pending.
1 = Endpoint6 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR6:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP6INT is a sticky bit. Interrupt remains valid until EP6INT is cleared by writing in the corresponding USB_CSR6 bit.
7UDP_EPINT7
AT91C_UDP_EPINT7
Endpoint 7 Interrupt
0 = No Endpoint7 Interrupt pending.
1 = Endpoint7 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR7:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP7INT is a sticky bit. Interrupt remains valid until EP7INT is cleared by writing in the corresponding USB_CSR7 bit.
8UDP_RXSUSP
AT91C_UDP_RXSUSP
USB Suspend Interrupt
0 = No USB Suspend Interrupt pending.
1 = USB Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
9UDP_RXRSM
AT91C_UDP_RXRSM
USB Resume Interrupt
0 = No USB Resume Interrupt pending.
1 =USB Resume Interrupt has been raised.
The USB device sets this bit when a USB resume signal is detected at its port.
10UDP_EXTRSM
AT91C_UDP_EXTRSM
USB External Resume Interrupt
0 = No External Resume Interrupt pending.
1 = External Resume Interrupt has been raised.
This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.
11UDP_SOFINT
AT91C_UDP_SOFINT
USB Start Of frame Interrupt
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.
13UDP_WAKEUP
AT91C_UDP_WAKEUP
USB Resume Interrupt
0 = No Wakeup Interrupt pending.
1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.

UDP: AT91_REG UDP_IMR - Interrupt Mask Register

Offset Name Description
0UDP_EPINT0
AT91C_UDP_EPINT0
Endpoint 0 Interrupt
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.
1UDP_EPINT1
AT91C_UDP_EPINT1
Endpoint 0 Interrupt
0 = No Endpoint1 Interrupt pending.
1 = Endpoint1 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.
2UDP_EPINT2
AT91C_UDP_EPINT2
Endpoint 2 Interrupt
0 = No Endpoint2 Interrupt pending.
1 = Endpoint2 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.
3UDP_EPINT3
AT91C_UDP_EPINT3
Endpoint 3 Interrupt
0 = No Endpoint3 Interrupt pending.
1 = Endpoint3 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR3:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit.
4UDP_EPINT4
AT91C_UDP_EPINT4
Endpoint 4 Interrupt
0 = No Endpoint4 Interrupt pending.
1 = Endpoint4 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR4:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit.
5UDP_EPINT5
AT91C_UDP_EPINT5
Endpoint 5 Interrupt
0 = No Endpoint5 Interrupt pending.
1 = Endpoint5 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR5:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit.
6UDP_EPINT6
AT91C_UDP_EPINT6
Endpoint 6 Interrupt
0 = No Endpoint6 Interrupt pending.
1 = Endpoint6 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR6:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP6INT is a sticky bit. Interrupt remains valid until EP6INT is cleared by writing in the corresponding USB_CSR6 bit.
7UDP_EPINT7
AT91C_UDP_EPINT7
Endpoint 7 Interrupt
0 = No Endpoint7 Interrupt pending.
1 = Endpoint7 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR7:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP7INT is a sticky bit. Interrupt remains valid until EP7INT is cleared by writing in the corresponding USB_CSR7 bit.
8UDP_RXSUSP
AT91C_UDP_RXSUSP
USB Suspend Interrupt
0 = No USB Suspend Interrupt pending.
1 = USB Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
9UDP_RXRSM
AT91C_UDP_RXRSM
USB Resume Interrupt
0 = No USB Resume Interrupt pending.
1 =USB Resume Interrupt has been raised.
The USB device sets this bit when a USB resume signal is detected at its port.
10UDP_EXTRSM
AT91C_UDP_EXTRSM
USB External Resume Interrupt
0 = No External Resume Interrupt pending.
1 = External Resume Interrupt has been raised.
This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.
11UDP_SOFINT
AT91C_UDP_SOFINT
USB Start Of frame Interrupt
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.
13UDP_WAKEUP
AT91C_UDP_WAKEUP
USB Resume Interrupt
0 = No Wakeup Interrupt pending.
1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.

UDP: AT91_REG UDP_ISR - Interrupt Status Register

Offset Name Description
0UDP_EPINT0
AT91C_UDP_EPINT0
Endpoint 0 Interrupt
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.
1UDP_EPINT1
AT91C_UDP_EPINT1
Endpoint 0 Interrupt
0 = No Endpoint1 Interrupt pending.
1 = Endpoint1 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.
2UDP_EPINT2
AT91C_UDP_EPINT2
Endpoint 2 Interrupt
0 = No Endpoint2 Interrupt pending.
1 = Endpoint2 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.
3UDP_EPINT3
AT91C_UDP_EPINT3
Endpoint 3 Interrupt
0 = No Endpoint3 Interrupt pending.
1 = Endpoint3 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR3:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit.
4UDP_EPINT4
AT91C_UDP_EPINT4
Endpoint 4 Interrupt
0 = No Endpoint4 Interrupt pending.
1 = Endpoint4 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR4:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit.
5UDP_EPINT5
AT91C_UDP_EPINT5
Endpoint 5 Interrupt
0 = No Endpoint5 Interrupt pending.
1 = Endpoint5 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR5:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit.
6UDP_EPINT6
AT91C_UDP_EPINT6
Endpoint 6 Interrupt
0 = No Endpoint6 Interrupt pending.
1 = Endpoint6 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR6:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP6INT is a sticky bit. Interrupt remains valid until EP6INT is cleared by writing in the corresponding USB_CSR6 bit.
7UDP_EPINT7
AT91C_UDP_EPINT7
Endpoint 7 Interrupt
0 = No Endpoint7 Interrupt pending.
1 = Endpoint7 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR7:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP7INT is a sticky bit. Interrupt remains valid until EP7INT is cleared by writing in the corresponding USB_CSR7 bit.
8UDP_RXSUSP
AT91C_UDP_RXSUSP
USB Suspend Interrupt
0 = No USB Suspend Interrupt pending.
1 = USB Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
9UDP_RXRSM
AT91C_UDP_RXRSM
USB Resume Interrupt
0 = No USB Resume Interrupt pending.
1 =USB Resume Interrupt has been raised.
The USB device sets this bit when a USB resume signal is detected at its port.
10UDP_EXTRSM
AT91C_UDP_EXTRSM
USB External Resume Interrupt
0 = No External Resume Interrupt pending.
1 = External Resume Interrupt has been raised.
This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.
11UDP_SOFINT
AT91C_UDP_SOFINT
USB Start Of frame Interrupt
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.
12UDP_ENDBUSRES
AT91C_UDP_ENDBUSRES
USB End Of Bus Reset Interrupt
0 = No End of Bus Reset Interrupt pending.
1 = End of Bus Reset Interrupt has been raised.
This interrupt is raised at the end of a USB reset sequence. The USB device must prepare to receive requests on the end-point 0. The host will start the enumeration, then will perform the configuration.
13UDP_WAKEUP
AT91C_UDP_WAKEUP
USB Resume Interrupt
0 = No Wakeup Interrupt pending.
1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.

UDP: AT91_REG UDP_ICR - Interrupt Clear Register

Offset Name Description
0UDP_EPINT0
AT91C_UDP_EPINT0
Endpoint 0 Interrupt
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit.
1UDP_EPINT1
AT91C_UDP_EPINT1
Endpoint 0 Interrupt
0 = No Endpoint1 Interrupt pending.
1 = Endpoint1 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR1:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit.
2UDP_EPINT2
AT91C_UDP_EPINT2
Endpoint 2 Interrupt
0 = No Endpoint2 Interrupt pending.
1 = Endpoint2 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR2:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit.
3UDP_EPINT3
AT91C_UDP_EPINT3
Endpoint 3 Interrupt
0 = No Endpoint3 Interrupt pending.
1 = Endpoint3 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR3:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit.
4UDP_EPINT4
AT91C_UDP_EPINT4
Endpoint 4 Interrupt
0 = No Endpoint4 Interrupt pending.
1 = Endpoint4 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR4:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit.
5UDP_EPINT5
AT91C_UDP_EPINT5
Endpoint 5 Interrupt
0 = No Endpoint5 Interrupt pending.
1 = Endpoint5 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR5:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit.
6UDP_EPINT6
AT91C_UDP_EPINT6
Endpoint 6 Interrupt
0 = No Endpoint6 Interrupt pending.
1 = Endpoint6 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR6:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP6INT is a sticky bit. Interrupt remains valid until EP6INT is cleared by writing in the corresponding USB_CSR6 bit.
7UDP_EPINT7
AT91C_UDP_EPINT7
Endpoint 7 Interrupt
0 = No Endpoint7 Interrupt pending.
1 = Endpoint7 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading USB_CSR7:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP7INT is a sticky bit. Interrupt remains valid until EP7INT is cleared by writing in the corresponding USB_CSR7 bit.
8UDP_RXSUSP
AT91C_UDP_RXSUSP
USB Suspend Interrupt
0 = No USB Suspend Interrupt pending.
1 = USB Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
9UDP_RXRSM
AT91C_UDP_RXRSM
USB Resume Interrupt
0 = No USB Resume Interrupt pending.
1 =USB Resume Interrupt has been raised.
The USB device sets this bit when a USB resume signal is detected at its port.
10UDP_EXTRSM
AT91C_UDP_EXTRSM
USB External Resume Interrupt
0 = No External Resume Interrupt pending.
1 = External Resume Interrupt has been raised.
This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus.
11UDP_SOFINT
AT91C_UDP_SOFINT
USB Start Of frame Interrupt
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.
13UDP_WAKEUP
AT91C_UDP_WAKEUP
USB Resume Interrupt
0 = No Wakeup Interrupt pending.
1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.

UDP: AT91_REG UDP_RSTEP - Reset Endpoint Register

Offset Name Description
0UDP_EP0
AT91C_UDP_EP0
Reset Endpoint 0
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR0.
1UDP_EP1
AT91C_UDP_EP1
Reset Endpoint 1
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR1.
2UDP_EP2
AT91C_UDP_EP2
Reset Endpoint 2
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR2.
3UDP_EP3
AT91C_UDP_EP3
Reset Endpoint 3
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR3.
4UDP_EP4
AT91C_UDP_EP4
Reset Endpoint 4
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR4.
5UDP_EP5
AT91C_UDP_EP5
Reset Endpoint 5
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR5.
6UDP_EP6
AT91C_UDP_EP6
Reset Endpoint 6
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR6.
7UDP_EP7
AT91C_UDP_EP7
Reset Endpoint 7
0 = No effect.
1 = Reset endpoint.
Endpoint reset clears all flags in USB_CSR7.

UDP: AT91_REG UDP_CSR - Endpoint Control and Status Register

Offset Name Description
0UDP_TXCOMP
AT91C_UDP_TXCOMP
Generates an IN packet with data previously written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware)
0 = Clear the flag, clear the interrupt.
1 = No effect.
Read (Set by the USB peripheral)
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTREADY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction.
1UDP_RX_DATA_BK0
AT91C_UDP_RX_DATA_BK0
Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware)
0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.
1 = No effect.
Read (Set by the USB peripheral)
0 = No data packet has been received in the FIFO's Bank 0
1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the USB_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0.
2UDP_RXSETUP
AT91C_UDP_RXSETUP
Sends STALL to the Host (Control endpoints)
This flag generates an interrupt while it is set to one.
Read
0 = No setup packet available.
1 = A setup data packet has been sent by the host and is available in the FIFO.
Write
0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1 = No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success-fully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the USB_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.
Ensuing Data OUT transactions will not be accepted while RXSETUP is set.
3UDP_ISOERROR
AT91C_UDP_ISOERROR
Isochronous error (Isochronous endpoints)
A CRC error has been detected in an isochronous transfer
Read
0 = No error in the previous isochronous transfer.
1 = CRC error has been detected, data available in the FIFO are corrupted.
Write
0 = reset the ISOERROR flag, clear the interrupt.
1 = No effect.
4UDP_TXPKTRDY
AT91C_UDP_TXPKTRDY
Transmit Packet Ready
This flag is cleared by the USB device.
This flag is set by the USB device firmware.
Read
0 = Data values can be written in the FIFO.
1 = Data values can not be written in the FIFO.
Write
0 = No effect.
1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent.
This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTREADY is cleared. Transfer to the FIFO is done by writing in the USB_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTREADY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host.
5UDP_FORCESTALL
AT91C_UDP_FORCESTALL
Force Stall (used by Control, Bulk and Isochronous endpoints).
Write-only
0 = No effect.
1 = Send STALL to the host.
Please refer to chapters 8.4.4 and 9.4.5 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the STALL handshake.
Control endpoints: during the data stage and status stage, this indicates that the microcontroller can not complete the request.
Bulk and interrupt endpoints: notify the host that the endpoint is halted.
The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.
6UDP_RX_DATA_BK1
AT91C_UDP_RX_DATA_BK1
Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware)
0 = Notify USB device that data have been read in the FIFO’s Bank 1.
1 = No effect.
Read (Set by the USB peripheral)
0 = No data packet has been received in the FIFO's Bank 1.
1 = A data packet has been received, it has been stored in FIFO's Bank 1.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through USB_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clear-ing RX_DATA_BK1.
7UDP_DIR
AT91C_UDP_DIR
Transfer Direction
0 = Allow Data OUT transactions in the control data stage.
1 = Enable Data IN transactions in the control data stage.
Please refer to Chapter 8.5.2 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the control data stage.
This bit must be set after the end of the setup stage. According to the request sent in the setup data packet, the data stage
will either be a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage.
10..8UDP_EPTYPE
AT91C_UDP_EPTYPE
Endpoint type
ValueLabelDescription
0UDP_EPTYPE_CTRL
AT91C_UDP_EPTYPE_CTRL

Control
1UDP_EPTYPE_ISO_OUT
AT91C_UDP_EPTYPE_ISO_OUT

Isochronous OUT
2UDP_EPTYPE_BULK_OUT
AT91C_UDP_EPTYPE_BULK_OUT

Bulk OUT
3UDP_EPTYPE_INT_OUT
AT91C_UDP_EPTYPE_INT_OUT

Interrupt OUT
5UDP_EPTYPE_ISO_IN
AT91C_UDP_EPTYPE_ISO_IN

Isochronous IN
6UDP_EPTYPE_BULK_IN
AT91C_UDP_EPTYPE_BULK_IN

Bulk IN
7UDP_EPTYPE_INT_IN
AT91C_UDP_EPTYPE_INT_IN

Interrupt IN
11UDP_DTGLE
AT91C_UDP_DTGLE
Data Toggle
Read-only
0 = Identifies DATA0 packet.
1 = Identifies DATA1 packet.
Please refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on DATA0, DATA1 packet definitions.
15UDP_EPEDS
AT91C_UDP_EPEDS
Endpoint Enable Disable
Read
0 = Endpoint disabled.
1 = Endpoint enabled.
Write
0 = Disable endpoint.
1 = Enable endpoint.
26..16UDP_RXBYTECNT
AT91C_UDP_RXBYTECNT
Number Of Bytes Available in the FIFO
Read-only.
When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontrol-ler. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the USB_FDRx register.

UDP: AT91_REG UDP_FDR - Endpoint FIFO Data Register


FIFO data value.
The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding USB_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Please refer to the Universal Serial Bus Specification, Rev. 1.1 to get more information.