USART Peripheral

US1 (AT91S_USART) 0xFFFC4000 (AT91C_BASE_US1)
Periph ID AIC Symbol Description
7 (AT91C_ID_US1)USART 1

Signal Symbol PIO controller Description
RXD1(AT91C_PA21_RXD1 )PIOA Periph: A Bit: 21USART 1 Receive Data
DTR1(AT91C_PA27_DTR1 )PIOA Periph: A Bit: 27USART 1 Data Terminal ready
DCD1(AT91C_PA26_DCD1 )PIOA Periph: A Bit: 26USART 1 Data Carrier Detect
TXD1(AT91C_PA22_TXD1 )PIOA Periph: A Bit: 22USART 1 Transmit Data
RTS1(AT91C_PA24_RTS1 )PIOA Periph: A Bit: 24USART 1 Ready To Send
SCK1(AT91C_PA23_SCK1 )PIOA Periph: A Bit: 23USART 1 Serial Clock
DSR1(AT91C_PA28_DSR1 )PIOA Periph: A Bit: 28USART 1 Data Set ready
RI1(AT91C_PA29_RI1 )PIOA Periph: A Bit: 29USART 1 Ring Indicator
CTS1(AT91C_PA25_CTS1 )PIOA Periph: A Bit: 25USART 1 Clear To Send

Function Description
AT91F_US1_CfgPMCEnable Peripheral clock in PMC for US1
AT91F_US1_CfgPIOConfigure PIO controllers to drive US1 signals


US0 (AT91S_USART) 0xFFFC0000 (AT91C_BASE_US0)
Periph ID AIC Symbol Description
6 (AT91C_ID_US0)USART 0

Signal Symbol PIO controller Description
RXD0(AT91C_PA5_RXD0 )PIOA Periph: A Bit: 5USART 0 Receive Data
TXD0(AT91C_PA6_TXD0 )PIOA Periph: A Bit: 6USART 0 Transmit Data
RTS0(AT91C_PA7_RTS0 )PIOA Periph: A Bit: 7USART 0 Ready To Send
SCK0(AT91C_PA2_SCK0 )PIOA Periph: B Bit: 2USART 0 Serial Clock
CTS0(AT91C_PA8_CTS0 )PIOA Periph: A Bit: 8USART 0 Clear To Send

Function Description
AT91F_US0_CfgPMCEnable Peripheral clock in PMC for US0
AT91F_US0_CfgPIOConfigure PIO controllers to drive US0 signals


USART Software API (AT91S_USART)

Offset Field Description
0x0US_CRControl Register
0x4US_MRMode Register
0x8US_IERInterrupt Enable Register
0xCUS_IDRInterrupt Disable Register
0x10US_IMRInterrupt Mask Register
0x14US_CSRChannel Status Register
0x18US_RHRReceiver Holding Register
0x1CUS_THRTransmitter Holding Register
0x20US_BRGRBaud Rate Generator Register
0x24US_RTORReceiver Time-out Register
0x28US_TTGRTransmitter Time-guard Register
0x40US_FIDIFI_DI_Ratio Register
0x44US_NERNb Errors Register
0x48US_XXRXON_XOFF Register
0x4CUS_IFIRDA_FILTER Register
0x100US_RPR (PDC_RPR)Receive Pointer Register
0x104US_RCR (PDC_RCR)Receive Counter Register
0x108US_TPR (PDC_TPR)Transmit Pointer Register
0x10CUS_TCR (PDC_TCR)Transmit Counter Register
0x110US_RNPR (PDC_RNPR)Receive Next Pointer Register
0x114US_RNCR (PDC_RNCR)Receive Next Counter Register
0x118US_TNPR (PDC_TNPR)Transmit Next Pointer Register
0x11CUS_TNCR (PDC_TNCR)Transmit Next Counter Register
0x120US_PTCR (PDC_PTCR)PDC Transfer Control Register
0x124US_PTSR (PDC_PTSR)PDC Transfer Status Register

Function Description
AT91F_US_EnableItEnable USART IT
AT91F_US_TxReadyReturn 1 if a character can be written in US_THR
AT91F_US_BaudrateCaluculate baud_value according to the main clock and the baud rate
AT91F_US_SetBaudrateSet the baudrate according to the CPU clock
AT91F_US_SendFrameReturn 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
AT91F_US_DisableRxDisable Receiver
AT91F_US_CloseClose USART: disable IT disable receiver and transmitter, close PDC
AT91F_US_DisableTxDisable Transmitter
AT91F_US_SetIrdaFilterSet the value of IrDa filter tregister
AT91F_US_RxReadyReturn 1 if a character can be read in US_RHR
AT91F_US_SetTimeguardSet USART timeguard
AT91F_US_DisableItDisable USART IT
AT91F_US_EnableRxEnable receiving characters
AT91F_US_EnableTxEnable sending characters
AT91F_US_ConfigureConfigure USART
AT91F_US_ResetRxReset Receiver and re-enable it
AT91F_US_ReceiveFrameReturn 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
AT91F_US_GetCharReceive a character,does not check if a character is available
AT91F_US_PutCharSend a character,does not check if ready to send
AT91F_US_ResetTxReset Transmitter and re-enable it
AT91F_US_ErrorReturn the error flag

USART Register Description

USART: AT91_REG US_CR - Control Register

Offset Name Description
2US_RSTRX
AT91C_US_RSTRX
Reset Receiver
0 = No effect.
1 = The receiver logic is reset, disabling the receive function (RXDIS is set internally).
3US_RSTTX
AT91C_US_RSTTX
Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset, disabling the transmit function (TXDIS and STPBRK are set internally).
4US_RXEN
AT91C_US_RXEN
Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
5US_RXDIS
AT91C_US_RXDIS
Receiver Disable
0 = No effect.
1 = The receiver is disabled.
6US_TXEN
AT91C_US_TXEN
Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
7US_TXDIS
AT91C_US_TXDIS
Transmitter Disable
0 = No effect.
1 = The transmitter is disabled.
8US_RSTSTA
AT91C_US_RSTSTA
Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.
9US_STTBRK
AT91C_US_STTBRK
Start Break
0 = No effect.
1 = If break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted.
10US_STPBRK
AT91C_US_STPBRK
Stop Break
0 = No effect.
1 = If a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12-bit periods.
11US_STTTO
AT91C_US_STTTO
Start Time-out
0 = No effect
1 = Start waiting for a character before clocking the time-out counter.
12US_SENDA
AT91C_US_SENDA
Send Address
0 = No effect.
1 = In Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set.
13US_RSTIT
AT91C_US_RSTIT
Reset Iterations
Note: This bit only has an effect in ISO7816 Mode.
0 = No effect.
1 = Resets the status bit Iteration.
14US_RSTNACK
AT91C_US_RSTNACK
Reset Non Acknowledge
0 = No effect
1 = Resets the status bit Nack
15US_RETTO
AT91C_US_RETTO
Rearm Time-out
0 = No effect
1 = Restart Time-out
16US_DTREN
AT91C_US_DTREN
Data Terminal ready Enable
0 = No effect.
1 = The DTR pin is forced to 0.
17US_DTRDIS
AT91C_US_DTRDIS
Data Terminal ready Disable
0 = No effect.
1 = The DTR pin is forced to 1.
18US_RTSEN
AT91C_US_RTSEN
Request to Send enable
0 = No effect.
1 = The RTS pin is forced to 0.
19US_RTSDIS
AT91C_US_RTSDIS
Request to Send Disable
0 = No effect.
1 = The RTS pin is forced to 1.

USART: AT91_REG US_MR - Mode Register

Offset Name Description
3..0US_USMODE
AT91C_US_USMODE
USART mode
The Baud Rate Clock used in mode IS07816 can be configured via the register FI_DI_RATIO.
ValueLabelDescription
0US_USMODE_NORMAL
AT91C_US_USMODE_NORMAL

Normal
1US_USMODE_RS485
AT91C_US_USMODE_RS485

RS485
2US_USMODE_HWHSH
AT91C_US_USMODE_HWHSH

Hardware Handshaking
3US_USMODE_MODEM
AT91C_US_USMODE_MODEM

Modem
4US_USMODE_ISO7816_0
AT91C_US_USMODE_ISO7816_0

ISO7816 protocol: T = 0
6US_USMODE_ISO7816_1
AT91C_US_USMODE_ISO7816_1

ISO7816 protocol: T = 1
8US_USMODE_IRDA
AT91C_US_USMODE_IRDA

IrDA
12US_USMODE_SWHSH
AT91C_US_USMODE_SWHSH

Software Handshaking
5..4US_CLKS
AT91C_US_CLKS
Clock Selection (Baud Rate generator Input Clock
ValueLabelDescription
0US_CLKS_CLOCK
AT91C_US_CLKS_CLOCK

Clock
1US_CLKS_FDIV1
AT91C_US_CLKS_FDIV1

fdiv1
2US_CLKS_SLOW
AT91C_US_CLKS_SLOW

slow_clock (ARM)
3US_CLKS_EXT
AT91C_US_CLKS_EXT

External (SCK)
7..6US_CHRL
AT91C_US_CHRL
Clock Selection (Baud Rate generator Input Clock
Start, stop and parity bits are added to the character length.
ValueLabelDescription
0US_CHRL_5_BITS
AT91C_US_CHRL_5_BITS

Character Length: 5 bits
1US_CHRL_6_BITS
AT91C_US_CHRL_6_BITS

Character Length: 6 bits
2US_CHRL_7_BITS
AT91C_US_CHRL_7_BITS

Character Length: 7 bits
3US_CHRL_8_BITS
AT91C_US_CHRL_8_BITS

Character Length: 8 bits
8US_SYNC
AT91C_US_SYNC
Synchronous Mode Select
0 = USART operates in Asynchronous Mode.
1 = USART operates in Synchronous Mode
11..9US_PAR
AT91C_US_PAR
Parity type
When the PAR field is set to Even parity, the parity bit is set (“1”) if the data parity is Odd in order to ensure an even parity on the Data and Parity field.
ValueLabelDescription
0US_PAR_EVEN
AT91C_US_PAR_EVEN

Even Parity
1US_PAR_ODD
AT91C_US_PAR_ODD

Odd Parity
2US_PAR_SPACE
AT91C_US_PAR_SPACE

Parity forced to 0 (Space)
3US_PAR_MARK
AT91C_US_PAR_MARK

Parity forced to 1 (Mark)
4US_PAR_NONE
AT91C_US_PAR_NONE

No Parity
6US_PAR_MULTI_DROP
AT91C_US_PAR_MULTI_DROP

Multi-drop mode
13..12US_NBSTOP
AT91C_US_NBSTOP
Number of Stop bits
The interpretation of the number of stop bits depends on SYNC.
1.5 or 2 stop bits are reserved for the TX function. The RX function uses only the 1 stop bit (there is no check on the 2 stop bit time slot if NBSTOP = 10).
ValueLabelDescription
0US_NBSTOP_1_BIT
AT91C_US_NBSTOP_1_BIT

1 stop bit
1US_NBSTOP_15_BIT
AT91C_US_NBSTOP_15_BIT

Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
2US_NBSTOP_2_BIT
AT91C_US_NBSTOP_2_BIT

2 stop bits
15..14US_CHMODE
AT91C_US_CHMODE
Channel Mode
ValueLabelDescription
0US_CHMODE_NORMAL
AT91C_US_CHMODE_NORMAL

Normal Mode: The USART channel operates as an RX/TX USART.
1US_CHMODE_AUTO
AT91C_US_CHMODE_AUTO

Automatic Echo: Receiver Data Input is connected to the TXD pin.
2US_CHMODE_LOCAL
AT91C_US_CHMODE_LOCAL

Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
3US_CHMODE_REMOTE
AT91C_US_CHMODE_REMOTE

Remote Loopback: RXD pin is internally connected to TXD pin.
16US_MSBF
AT91C_US_MSBF
Bit Order
0 = LSB First
1 = MSB First
17US_MODE9
AT91C_US_MODE9
9-bit Character length
0 = CHRL defines character length.
1 = 9-bit character length.
MODE9 has priority on character length.
18US_CKLO
AT91C_US_CKLO
Clock Output Select
0 = The USART does not drive the SCK pin.
1 = The USART drives the SCK pin if USCLKS[1] is 0.
19US_OVER
AT91C_US_OVER
Over Sampling Mode
0 = 16x Oversampling
1 = 8x Oversampling
20US_INACK
AT91C_US_INACK
Inhibit Non Acknowledge
0 = The NACK is generated
1 = The NACK is not generated
Note: This bit will be used only in ISO7816 mode, protocol T = 0 receiver.
21US_DSNACK
AT91C_US_DSNACK
Disable Successive NACK
0 = NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1 = Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.
24US_MAX_ITER
AT91C_US_MAX_ITER
Number of Repetitions
0-7 This will operate in mode ISO7816, Protocol T=0 only
28US_FILTER
AT91C_US_FILTER
Receive Line Filter
0 = The USART does not filter the receive line.
1 = The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

USART: AT91_REG US_IER - Interrupt Enable Register

Offset Name Description
0US_RXRDY
AT91C_US_RXRDY
RXRDY Interrupt
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
1US_TXRDY
AT91C_US_TXRDY
TXRDY Interrupt
0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1 = There is no character in the US_THR.
Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
2US_RXBRK
AT91C_US_RXBRK
Break Received/End of Break
0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
3US_ENDRX
AT91C_US_ENDRX
End of Receive Transfer Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4US_ENDTX
AT91C_US_ENDTX
End of Transmit Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5US_OVRE
AT91C_US_OVRE
Overrun Interrupt
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6US_FRAME
AT91C_US_FRAME
Framing Error Interrupt
0 = No stop bit has been detected low since the last Reset Status Bits command.
1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7US_PARE
AT91C_US_PARE
Parity Error Interrupt
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
8US_TIMEOUT
AT91C_US_TIMEOUT
Receiver Time-out
0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.
1 = There has been a time-out since the last Start Time-out command.
9US_TXEMPTY
AT91C_US_TXEMPTY
TXEMPTY Interrupt
0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.
Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
10US_ITERATION
AT91C_US_ITERATION
Max number of Repetitions Reached
Note: This bit will operate only in IS07816 mode, Protocol T = 0.
0 = Max number of repetitions has not been reached.
1 = Max number of repetitions has been reached.
A repetition consists of transmitted characters or successive NACK.
11US_TXBUFE
AT91C_US_TXBUFE
TXBUFE Interrupt
0 = PDC2 Transmission Buffer is not empty.
1 = PDC2 Transmission Buffer is empty
12US_RXBUFF
AT91C_US_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.
13US_NACK
AT91C_US_NACK
Non Acknowledge
0 = A Non Acknowledge has not been detected.
1 = A Non Acknowledge has been detected.
16US_RIIC
AT91C_US_RIIC
Ring INdicator Input Change Flag
0 = No input change has been detected on the RI pin since the last read of US_CSR.
1 = An input change has been detected on the RI pin.
17US_DSRIC
AT91C_US_DSRIC
Data Set Ready Input Change Flag
0 = No input change has been detected on the DSR pin since the last read of US_CSR.
1 = An input change has been detected on the DSR pin.
18US_DCDIC
AT91C_US_DCDIC
Data Carrier Flag
0 = No input change has been detected on the DCD pin since the last read of US_CSR.
1 = An input change has been detected on the DCD pin.
19US_CTSIC
AT91C_US_CTSIC
Clear To Send Input Change Flag
0 = No input change has been detected on the CTS pin since the last read of US_CSR.
1 = An input change has been detected on the CTS pin.
30US_COMM_TX
AT91C_US_COMM_TX
Mask COMM_TX Interrupt
0 = COMM_TX is at 0.
1 = COMM_TX is at 1.
31US_COMM_RX
AT91C_US_COMM_RX
Mask COMM_RX Interrupt
0 = COMM_RX is at 0.
1 = COMM_RX is at 1.

USART: AT91_REG US_IDR - Interrupt Disable Register

Offset Name Description
0US_RXRDY
AT91C_US_RXRDY
RXRDY Interrupt
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
1US_TXRDY
AT91C_US_TXRDY
TXRDY Interrupt
0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1 = There is no character in the US_THR.
Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
2US_RXBRK
AT91C_US_RXBRK
Break Received/End of Break
0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
3US_ENDRX
AT91C_US_ENDRX
End of Receive Transfer Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4US_ENDTX
AT91C_US_ENDTX
End of Transmit Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5US_OVRE
AT91C_US_OVRE
Overrun Interrupt
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6US_FRAME
AT91C_US_FRAME
Framing Error Interrupt
0 = No stop bit has been detected low since the last Reset Status Bits command.
1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7US_PARE
AT91C_US_PARE
Parity Error Interrupt
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
8US_TIMEOUT
AT91C_US_TIMEOUT
Receiver Time-out
0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.
1 = There has been a time-out since the last Start Time-out command.
9US_TXEMPTY
AT91C_US_TXEMPTY
TXEMPTY Interrupt
0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.
Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
10US_ITERATION
AT91C_US_ITERATION
Max number of Repetitions Reached
Note: This bit will operate only in IS07816 mode, Protocol T = 0.
0 = Max number of repetitions has not been reached.
1 = Max number of repetitions has been reached.
A repetition consists of transmitted characters or successive NACK.
11US_TXBUFE
AT91C_US_TXBUFE
TXBUFE Interrupt
0 = PDC2 Transmission Buffer is not empty.
1 = PDC2 Transmission Buffer is empty
12US_RXBUFF
AT91C_US_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.
13US_NACK
AT91C_US_NACK
Non Acknowledge
0 = A Non Acknowledge has not been detected.
1 = A Non Acknowledge has been detected.
16US_RIIC
AT91C_US_RIIC
Ring INdicator Input Change Flag
0 = No input change has been detected on the RI pin since the last read of US_CSR.
1 = An input change has been detected on the RI pin.
17US_DSRIC
AT91C_US_DSRIC
Data Set Ready Input Change Flag
0 = No input change has been detected on the DSR pin since the last read of US_CSR.
1 = An input change has been detected on the DSR pin.
18US_DCDIC
AT91C_US_DCDIC
Data Carrier Flag
0 = No input change has been detected on the DCD pin since the last read of US_CSR.
1 = An input change has been detected on the DCD pin.
19US_CTSIC
AT91C_US_CTSIC
Clear To Send Input Change Flag
0 = No input change has been detected on the CTS pin since the last read of US_CSR.
1 = An input change has been detected on the CTS pin.
30US_COMM_TX
AT91C_US_COMM_TX
Mask COMM_TX Interrupt
0 = COMM_TX is at 0.
1 = COMM_TX is at 1.
31US_COMM_RX
AT91C_US_COMM_RX
Mask COMM_RX Interrupt
0 = COMM_RX is at 0.
1 = COMM_RX is at 1.

USART: AT91_REG US_IMR - Interrupt Mask Register

Offset Name Description
0US_RXRDY
AT91C_US_RXRDY
RXRDY Interrupt
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
1US_TXRDY
AT91C_US_TXRDY
TXRDY Interrupt
0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1 = There is no character in the US_THR.
Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
2US_RXBRK
AT91C_US_RXBRK
Break Received/End of Break
0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
3US_ENDRX
AT91C_US_ENDRX
End of Receive Transfer Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4US_ENDTX
AT91C_US_ENDTX
End of Transmit Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5US_OVRE
AT91C_US_OVRE
Overrun Interrupt
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6US_FRAME
AT91C_US_FRAME
Framing Error Interrupt
0 = No stop bit has been detected low since the last Reset Status Bits command.
1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7US_PARE
AT91C_US_PARE
Parity Error Interrupt
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
8US_TIMEOUT
AT91C_US_TIMEOUT
Receiver Time-out
0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.
1 = There has been a time-out since the last Start Time-out command.
9US_TXEMPTY
AT91C_US_TXEMPTY
TXEMPTY Interrupt
0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.
Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
10US_ITERATION
AT91C_US_ITERATION
Max number of Repetitions Reached
Note: This bit will operate only in IS07816 mode, Protocol T = 0.
0 = Max number of repetitions has not been reached.
1 = Max number of repetitions has been reached.
A repetition consists of transmitted characters or successive NACK.
11US_TXBUFE
AT91C_US_TXBUFE
TXBUFE Interrupt
0 = PDC2 Transmission Buffer is not empty.
1 = PDC2 Transmission Buffer is empty
12US_RXBUFF
AT91C_US_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.
13US_NACK
AT91C_US_NACK
Non Acknowledge
0 = A Non Acknowledge has not been detected.
1 = A Non Acknowledge has been detected.
16US_RIIC
AT91C_US_RIIC
Ring INdicator Input Change Flag
0 = No input change has been detected on the RI pin since the last read of US_CSR.
1 = An input change has been detected on the RI pin.
17US_DSRIC
AT91C_US_DSRIC
Data Set Ready Input Change Flag
0 = No input change has been detected on the DSR pin since the last read of US_CSR.
1 = An input change has been detected on the DSR pin.
18US_DCDIC
AT91C_US_DCDIC
Data Carrier Flag
0 = No input change has been detected on the DCD pin since the last read of US_CSR.
1 = An input change has been detected on the DCD pin.
19US_CTSIC
AT91C_US_CTSIC
Clear To Send Input Change Flag
0 = No input change has been detected on the CTS pin since the last read of US_CSR.
1 = An input change has been detected on the CTS pin.
30US_COMM_TX
AT91C_US_COMM_TX
Mask COMM_TX Interrupt
0 = COMM_TX is at 0.
1 = COMM_TX is at 1.
31US_COMM_RX
AT91C_US_COMM_RX
Mask COMM_RX Interrupt
0 = COMM_RX is at 0.
1 = COMM_RX is at 1.

USART: AT91_REG US_CSR - Channel Status Register

Offset Name Description
0US_RXRDY
AT91C_US_RXRDY
RXRDY Interrupt
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
1US_TXRDY
AT91C_US_TXRDY
TXRDY Interrupt
0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1 = There is no character in the US_THR.
Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
2US_RXBRK
AT91C_US_RXBRK
Break Received/End of Break
0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.
3US_ENDRX
AT91C_US_ENDRX
End of Receive Transfer Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4US_ENDTX
AT91C_US_ENDTX
End of Transmit Interrupt
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5US_OVRE
AT91C_US_OVRE
Overrun Interrupt
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6US_FRAME
AT91C_US_FRAME
Framing Error Interrupt
0 = No stop bit has been detected low since the last Reset Status Bits command.
1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7US_PARE
AT91C_US_PARE
Parity Error Interrupt
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
8US_TIMEOUT
AT91C_US_TIMEOUT
Receiver Time-out
0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.
1 = There has been a time-out since the last Start Time-out command.
9US_TXEMPTY
AT91C_US_TXEMPTY
TXEMPTY Interrupt
0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.
Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
10US_ITERATION
AT91C_US_ITERATION
Max number of Repetitions Reached
Note: This bit will operate only in IS07816 mode, Protocol T = 0.
0 = Max number of repetitions has not been reached.
1 = Max number of repetitions has been reached.
A repetition consists of transmitted characters or successive NACK.
11US_TXBUFE
AT91C_US_TXBUFE
TXBUFE Interrupt
0 = PDC2 Transmission Buffer is not empty.
1 = PDC2 Transmission Buffer is empty
12US_RXBUFF
AT91C_US_RXBUFF
RXBUFF Interrupt
0 = PDC2 Reception Buffer is not full.
1 = PDC2 Reception Buffer is full.
13US_NACK
AT91C_US_NACK
Non Acknowledge
0 = A Non Acknowledge has not been detected.
1 = A Non Acknowledge has been detected.
16US_RIIC
AT91C_US_RIIC
Ring INdicator Input Change Flag
0 = No input change has been detected on the RI pin since the last read of US_CSR.
1 = An input change has been detected on the RI pin.
17US_DSRIC
AT91C_US_DSRIC
Data Set Ready Input Change Flag
0 = No input change has been detected on the DSR pin since the last read of US_CSR.
1 = An input change has been detected on the DSR pin.
18US_DCDIC
AT91C_US_DCDIC
Data Carrier Flag
0 = No input change has been detected on the DCD pin since the last read of US_CSR.
1 = An input change has been detected on the DCD pin.
19US_CTSIC
AT91C_US_CTSIC
Clear To Send Input Change Flag
0 = No input change has been detected on the CTS pin since the last read of US_CSR.
1 = An input change has been detected on the CTS pin.
20US_RI
AT91C_US_RI
Image of RI Input
0 = RI is at 0.
1 = RI is at 1.
21US_DSR
AT91C_US_DSR
Image of DSR Input
0 = DSR
1 = DSR is at 1.
22US_DCD
AT91C_US_DCD
Image of DCD Input
0 = DCD is at 0.
1 = DCD is at 1.
23US_CTS
AT91C_US_CTS
Image of CTS Input
0 = CTS is at 0.
1 = CTS is at 1.
30US_COMM_TX
AT91C_US_COMM_TX
Mask COMM_TX Interrupt
0 = COMM_TX is at 0.
1 = COMM_TX is at 1.
31US_COMM_RX
AT91C_US_COMM_RX
Mask COMM_RX Interrupt
0 = COMM_RX is at 0.
1 = COMM_RX is at 1.

USART: AT91_REG US_RHR - Receiver Holding Register


Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-sig-nificant bits read zero.

USART: AT91_REG US_THR - Transmitter Holding Register


Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned.

USART: AT91_REG US_BRGR - Baud Rate Generator Register


Clock Divisor:
0 Disables Clock
1 Clock Divisor Bypass
2 to 65535 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD)
Baud Rate (Synchronous Mode) = Selected Clock/CD
Notes: 1. In Synchronous Mode, when either external clock (clk_ext or fdiv1) is selected, the value programmed must be even to ensure a 50:50 mark:space ratio.
In Synchronous Mode, when the internal clock (clock) is selected, the CD can be even and the duty clock is 50:50.
2. Clock divisor bypass (CD = 1) must not be used when the internal clock (clock) is selected (USCLKS = 0).
3. In Asynchronous Mode, the divisor of Selected Clock depends upon the value of the bit, OVER in US_MR.

USART: AT91_REG US_RTOR - Receiver Time-out Register


Time-out Value:
0 Disables the RX Time-out function.
1-65535 The Time-out counter is loaded with TO (16 bits) when the Start Time-out command is given or when each new data character is received (after reception has started).

USART: AT91_REG US_TTGR - Transmitter Time-guard Register


Time-guard duration = TG x Bit Period:
0 Disables the TX Time-out function.
1-255 TXD is inactive high after the transmission of each character for the time-guard duration.

USART: AT91_REG US_FIDI - FI_DI_Ratio Register


Parameter used in mode ISO7816 to generate a specific bit rate
0 Baud Rate = 0
1-2047 Baud Rate = selected clock/FI_DI_RATIO/16

USART: AT91_REG US_NER - Nb Errors Register


This 8-bit register presents the total amount of errors that occurred during an ISO7816 transfer. It is a read-only register and it is reset by reading the register.

USART: AT91_REG US_XXR - XON_XOFF Register


Bits [15..8] XON character
Bits [7..0] XOFF character

USART: AT91_REG US_IF - IRDA_FILTER Register


0-155 Parameter to reject pulses on IrDa reception

USART: AT91S_PDC US_PDC - PDC interface